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RT600 Scheda tecnica(PDF) 21 Page - NXP Semiconductors |
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RT600 Scheda tecnica(HTML) 21 Page - NXP Semiconductors |
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21 / 167 page  RT600 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors B.V. 2022. All rights reserved. Product data sheet Rev. 2.0 — 1 April 2022 21 of 165 NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs PIO0_16 K5 D6 B12 Z I/O 0 PIO0_16 — General-purpose digital input/output pin. I/O 1 FC2_RXD_SDA_MOSI_DATA — Flexcomm 2: USART receiver, I2C data I/O, SPI master-out/slave-in data, I2S data I/O. I2 SCT0_GPI2 — Pin input 2 to SCTimer/PWM. O3 SCT0_OUT2 — SCTimer/PWM output 2. O4 CTIMER2_MAT2 — 32-bit CTimer2 match output 2. I5 I2S_BRIDGE_DATA_IN — Allows I2S bypass by re-routing this function to a pin that includes the I2S_BRIDGE_DATA_OUT function. 6 R — Reserved. 7 R — Reserved. I/O 8 SEC_PIO0_16 — Secure GPIO pin. PIO0_17 - D7 B14 Z I/O 0 PIO0_17 — General-purpose digital input/output pin. I/O 1 FC2_CTS_SDA_SSEL0 — Flexcomm 2: USART clear-to-send, I2C data I/O, SPI Slave Select 0. I2 SCT0_GPI3 — Pin input 3 to SCTimer/PWM. O3 SCT0_OUT3 — SCTimer/PWM output 3. O4 CTIMER2_MAT3 — 32-bit CTimer2 match output 3. I/O 5 FC5_SSEL2 — Flexcomm 5: SPI slave select 2. 6 R — Reserved. 7 R — Reserved. I/O 8 SEC_PIO0_17 — Secure GPIO pin. PIO0_18 - B7 A14 Z I/O 0 PIO0_18 — General-purpose digital input/output pin. I/O 1 FC2_RTS_SCL_SSEL1 — Flexcomm 2: USART request-to-send, I2C clock, SPI slave select 1. I2 SCT0_GPI6 — Pin input 6 to SCTimer/PWM. O3 SCT0_OUT6 — SCTimer/PWM output 6. I4 CTIMER_INP4 — Capture input 4 to CTIMER input muxes. I/O 5 FC5_SSEL3 — Flexcomm 5: SPI slave select 3. 6 R — Reserved. 7 R — Reserved. I/O 8 SEC_PIO0_18 — Secure GPIO pin. Table 4. Pin description …continued Symbol Description |
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