HT46R232 datasheet(8/50 Pages) HOLTEK

8 / 50 page

HT46R232/HT46C232

Rev. 1.40

November 23, 2005

value from the stack. After a chip reset, the SP will point

to the top of the stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledgment will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt is

serviced. This feature prevents stack overflow, allowing

the programmer to use the structure more easily. If the

stack is full and a

²CALL² is subsequently executed,

stack overflow occurs and the first entry will be lost (only

the most recent 8 return addresses are stored).

Data Memory - RAM

The data memory (RAM) is designed with 231

´8 bits,

and is divided into two functional groups, namely; spe-

cial function registers (39

´8 bits) and general purpose

data memory (192

´8 bits) most of which are read-

able/writeable, although some are read only.

The special function registers are overlapped in any

banks. Of the two types of functional groups, the special

function registers consist of an Indirect addressing reg-

ister 0 (00H), a Memory pointer register 0 (MP0;01H),

an Indirect addressing register 1 (02H), a Memory

pointer register 1 (MP1;03H), an Accumulator

(ACC;05H), a Program counter lower-order byte regis-

ter (PCL;06H), a Table pointer (TBLP;07H), a Table

higher-order byte register (TBLH;08H), a Status register

(STATUS;0AH), an Interrupt control register 0

(INTC0;0BH), a Timer/Event Counter 0 (TMR0H:0CH;

TMR0L:0DH), a Timer/Event Counter 0 control register

(TMR0C;0EH), a Timer/Event Counter 1 (TMR1H:0FH;

TMR1L:10H), a Timer/Event Counter 1 control register

(TMR1C; 11H), Interrupt control register 1 (INTC1;1EH),

PWM data register (PWM0;1AH, PWM1;1BH,

PWM2;1CH, PWM3;1DH), the I

2C Bus slave address

2C Bus control register

(HCR;21H), the I

2C Bus status register (HSR;22H), the

2C Bus data register (HDR;23H),the A/D result

lower-order byte register (ADRL;24H), the A/D result

higher-order byte register (ADRH;25H), the A/D control

(ACSR;27H), I/O registers (PA;12H, PB;14H, PC;16H,

PD;18H, PF; 28H) and I/O control registers (PAC;13H,

PBC;15H, PCC;17H, PDC;19H, PFC;29H). The remain-

ing space before the 40H is reserved for future ex-

panded usage and reading these locations will get

²00H². The space before 40H is overlapping in each

bank. The general purpose data memory, addressed

from 40H to FFH, is used for data and control informa-

tion under instruction commands.

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by

²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer registers (MP0;01H/MP1;03H). The

space before 40H is overlapping in each bank.

S p e c i a l P u r p o s e

D a t a M e m o r y

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

: U n u s e d

R e a d a s " 0 0 "

G e n e r a l P u r p o s e

D a t a M e m o r y

( 1 9 2 B y t e s )

F F H

4 0 H

2 0 H

2 1 H

2 2 H

2 3 H

2 4 H

2 5 H

2 6 H

2 7 H

2 8 H

2 9 H

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

M P 0

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

M P 1

A C C

P C L

T B L P

T B L H

S T A T U S

I N T C 0

T M R 0 H

T M R 0 L

T M R 0 C

T M R 1 H

T M R 1 L

T M R 1 C

P A

P A C

P B

P B C

P C

P C C

P D

P D C

P W M 0

P W M 1

P W M 2

P W M 3

I N T C 1

H A D R

H C R

H S R

H D R

A D R L

A D R H

A D C R

A C S R

P F

P F C

3 F H

3 0 H

RAM Mapping

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