HT46R232 datasheet(13/50 Pages) HOLTEK

13 / 50 page

HT46R232/HT46C232

Rev. 1.40

November 23, 2005

PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² stands for ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem awakes from the HALT state or during power up.

Awaking from the HALT state or system power up an

SST delay is added. An extra SST delay is added during

power up period, and any wake-up from HALT may en-

able only the SST delay. The functional unit chip reset

status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler, Divider

Cleared

WDT

Clear. After master reset,

WDT begins counting

Timer/event Counter

Off

Input/output Ports

Input mode

Stack Pointer

Points to the top of the stack

Timer/Event Counter

Two Timer/Event Counters (TMR0,TMR1) are imple-

mented in the microcontroller. The timer/event counter 0

contains an 16-bit programmable count-up counter and

the clock may come from an external source or an inter-

nal clock source. An internal clock source comes from

fSYS. The timer/event counter 1 contains an 16-bit pro-

grammable count-up counter and the clock may come

from an external source or an internal clock source. An

internal clock source comes from fSYS/4. The external

clock input allows the user to count external events,

measure time intervals or pulse widths, or to generate

an accurate time base.

There are six registers related to the Timer/Event Coun-

ter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH) and

the Timer/Event Counter 1; TMR1H (0FH), TMR1L

(10H), TMR1C (11H). Writing TMR0L (TMR1L) will only

put the written data to an internal lower-order byte buffer

(8-bit) and writing TMR0H (TMR1H) will transfer the

specified data and the contents of the lower-order byte

buffer to TMR0H (TMR1H) and TMR0L (TMR1L) regis-

ters, respectively. The Timer/Event Counter 1/0 preload

operations. Reading TMR0H (TMR1H) will latch the

contents of TMR0H (TMR1H) and TMR0L (TMR1L)

counters to the destination and the lower-order byte

buffer, respectively. Reading the TMR0L (TMR1L) will

read the contents of the lower-order byte buffer. The

TMR0C (TMR1C) is the Timer/Event Counter 0 (1) con-

trol register, which defines the operating mode, counting

enable or disable and an active edge.

The T0M0, T0M1 (TMR0C) and T1M0, T1M1 (TMR1C)

bits define the operation mode. The event count mode is

used to count external events, which means that the

clock source is from an external (TMR0, TMR1) pin. The

timer mode functions as a normal timer with the clock

source coming from the internal selected clock source.

Finally, the pulse width measurement mode can be used

to count the high or low level duration of the external sig-

nal (TMR0, TMR1), and the counting is based on the in-

ternal selected clock source.

In the event count or timer mode, the timer/event coun-

ter starts counting at the current contents in the

timer/event counter and ends at FFFFH. Once an over-

flow occurs, the counter is reloaded from the timer/event

counter preload register, and generates an interrupt re-

quest flag (T0F; bit 5 of INTC0, T1F; bit 6 of INTC0).

In the pulse width measurement mode with the values of

the T0ON/T1ON and T0E/T1E bits equal to 1, after the

TMR0 (TMR1) has received a transient from low to high

(or high to low if the T0E/T1E bit is

²0²), it will start count-

ing until the TMR0 (TMR1) returns to the original level

and resets the T0ON/T1ON. The measured result re-

mains in the timer/event counter even if the activated

transient occurs again. In other words, only 1-cycle

measurement can be made until the T0ON/T1ON is set.

The cycle measurement will re-function as long as it re-

ceives further transient pulse. In this operation mode,

the timer/event counter begins counting not according

to the logic level but to the transient edges. In the case of

counter overflows, the counter is reloaded from the

timer/event counter register and issues an interrupt re-

quest, as in the other two modes, i.e., event and timer

modes.

W a r m R e s e t

W D T

H A L T

C o l d

R e s e t

R E S

P o w e r - o n D e t e c t i o n

S S T

1 0 - b i t R i p p l e

C o u n t e r

O S C 1

W D T

E x t e r n a l

T i m e - o u t

R e s e t

Reset Configuration

t S S T + t O P D

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset Timing Chart

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