XIO2000 datasheet(129/150 Pages) TI

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Memory-Mapped TI Proprietary Register Space

117

November 2005

SCPS097B

6.18 GPIO Data Register

This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO

terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary

functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), GPIO4 (SCL), and GPIO5 (SDA). The default

value at power up depends on the state of the GPIO terminals as they default to general-purpose inputs. This

Section 4.60). See Table 6−9 for a complete description of the register contents.

Device control memory window register offset:

42h

Read-only, Read/Write

Default value:

00XXh

BIT NUMBER

RESET STATE

Table 6−9. GPIO Data Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:8

RSVD

Reserved. Returns 00h when read.

7†

GPIO7_Data

GPIO 7 data. This bit reads the state of GPIO7 when in input mode or changes the state of

GPIO7 when in output mode.

6†

GPIO6_Data

GPIO 6 data. This bit reads the state of GPIO6 when in input mode or changes the state of

GPIO6 when in output mode.

5†

GPIO5_Data

GPIO 5 data. This bit reads the state of GPIO5 when in input mode or changes the state of

GPIO5 when in output mode.

4†

GPIO4_Data

GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of

GPIO4 when in output mode.

3†

GPIO3_Data

GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of

GPIO3 when in output mode.

2†

GPIO2_Data

GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of

GPIO2 when in output mode.

1†

GPIO1_Data

GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of

GPIO1 when in output mode.

0†

GPIO0_Data

GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of

GPIO0 when in output mode.

† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

6.19 Serial-Bus Data Register

The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this

from the serial bus, this register contains the data read after bit 5 (REQBUSY) in the serial-bus control and

status register (offset 47h, see Section 6.22) is cleared. This register is an alias for the serial-bus data register

in the PCI header (offset B0h, see Section 4.55). This register is reset by a PCI Express reset (PERST), a

GRST, or the internally-generated power-on reset.

Device control memory window register offset:

44h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

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