XIO2000 datasheet(130/150 Pages) TI

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Memory-Mapped TI Proprietary Register Space

118

November 2005

SCPS097B

6.20 Serial-Bus Word Address Register

The value written to the serial-bus word address register represents the word address of the byte being read

from or written to on the serial-bus interface. The word address is loaded into this register prior to writing the

serial-bus slave address register that initiates the bus cycle. This register is an alias for the serial-bus word

address register in the PCI header (offset B1h, see Section 4.56). This register is reset by a PCI Express reset

(PERST), a GRST, or the internally-generated power-on reset.

Device control memory window register offset:

45h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

6.21 Serial-Bus Slave Address Register

The serial-bus slave address register indicates the address of the device being targeted by the serial-bus

cycle. This register also indicates if the cycle will be a read or a write cycle. Writing to this register initiates the

cycle on the serial interface. This register is an alias for the serial-bus slave address register in the PCI header

(offset B2h, see Section 4.57). See Table 6−10 for a complete description of the register contents.

Device control memory window register offset:

46h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

Table 6−10. Serial-Bus Slave Address Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:1†

SLAVE_ADDR

Serial-bus slave address. This 7-bit field is the slave address for a serial-bus read or write

transaction. The default value for this field is 000 0000b.

0†

RW_CMD

Read/write command. This bit determines if the serial-bus cycle is a read or a write cycle.

0 = A single byte write is requested (default)

1 = A single byte read is requested

† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

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