XIO2000 datasheet(133/150 Pages) TI

133 / 150 page

Memory-Mapped TI Proprietary Register Space

121

November 2005

SCPS097B

6.24 Serial IRQ Edge Control Register

This register controls the edge mode of each IRQ in the serial IRQ stream. This register is an alias for the serial

IRQ edge control register in the classic PCI configuration space (offset E2h, see Section 4.73). See

Table 6−13 for a complete description of the register contents.

Device control memory window register offset:

4Ah

Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 6−13. Serial IRQ Edge Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15†

IRQ15_MODE

IRQ 15 edge mode

0 = Edge mode (default)

1 = Level mode

14†

IRQ14_MODE

IRQ 14 edge mode

0 = Edge mode (default)

1 = Level mode

13†

IRQ13_MODE

IRQ 13 edge mode

0 = Edge mode (default)

1 = Level mode

12†

IRQ12_MODE

IRQ 12 edge mode

0 = Edge mode (default)

1 = Level mode

11†

IRQ11_MODE

IRQ 11 edge mode

0 = Edge mode (default)

1 = Level mode

10†

IRQ10_MODE

IRQ 10 edge mode

0 = Edge mode (default)

1 = Level mode

9†

IRQ9_MODE

IRQ 9 edge mode

0 = Edge mode (default)

1 = Level mode

8†

IRQ8_MODE

IRQ 8 edge mode

0 = Edge mode (default)

1 = Level mode

7†

IRQ7_MODE

IRQ 7 edge mode

0 = Edge mode (default)

1 = Level mode

6†

IRQ6_MODE

IRQ 6 edge mode

0 = Edge mode (default)

1 = Level mode

5†

IRQ5_MODE

IRQ 5 edge mode

0 = Edge mode (default)

1 = Level mode

4†

IRQ4_MODE

IRQ 4 edge mode

0 = Edge mode (default)

1 = Level mode

† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

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