AM486DX2 datasheet(29/67 Pages) AMD

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Am5X86 Microprocessor

AMD

PRELIMINARY

Data

HITM

EADS

INV

Read

BRDY

AHOLD

BLAST

ADS

W/R

M/IO

ADR

CLK

W n+4

W n

W n+8

W n+C

Figure 12. Snoop Hit Cycle with Write-Back

Note:

The circled numbers in this figure represent the steps in section 4.8.5.3.

CACHE

from CPU

to CPU

from CPU

Step 8 As an example, AHOLD is now removed. In the

next clock cycle, the current address of the

write-back access is driven onto the address

bus.

Step 9 The write-back access is finished when BLAST

and BRDY both transition to 0.

Step 10 In the clock cycle after the final write-back

access, the snooping cache drives HITM back

to 1.

The status of the snooped and written-back line is now

either shared (INV = 0) or is changed to invalid (INV = 1).

4.8.6

Reordering of Write-Backs (AHOLD) with

BOFF

As seen previously, the Bus Interface Unit (BIU) com-

pletes the processor-initiated access first if the snooping

access occurs after the start of the processor-initiated

access. If the HITM signal occurs one clock cycle before

the ADS = 0 of the processor-initiated access, the write-

back receives priority and is executed first.

However, if the snooping access is executed after the

start of the processor-initiated access, there is a

methodology to reorder the access order. The BOFF

signal delays outstanding processor-initiated cycles so

that a snoop write-back can occur immediately (see

Figure 13).

Scenario: If there are outstanding processor-initiated

cycles on the bus, asserting BOFF clears the bus pipe-

line. If a snoop causes HITM to be asserted, the first

cycle issued by the microprocessor after deassertion of

BOFF is the write-back cycle. After the write-back cycle,

it reissues the aborted cycles. This translates into the

following sequence:

Step 1 The processor starts a cacheable burst read

cycle.

Step 2 One clock cycle later, AHOLD is asserted. This

switches the address bus into an input one clock

cycle after AHOLD is asserted.

Step 3 Two clock cycles after AHOLD is asserted, the

EADS and INV signals are asserted to start the

snooping cycle.

Step 4 Two clock cycles after EADS is asserted, HITM

becomes valid. The line is modified, therefore

HITM = 0.

Step 5 Note that the processor-initiated access is not

completed because BLAST = 1.

Step 6 With HITM going Low, the core system logic

asserts BOFF in the next clock cycle to the

snooping processor to reorder the access.

BOFF overrides BRDY. Therefore, the partial

read is not used. It is reread later.

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