AM486DX2 datasheet(34/67 Pages) AMD

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Am5X86 Microprocessor

AMD

PRELIMINARY

4.9.3

Snooping During Cache Flushing

As with snooping during normal operation, snooping is

permitted during a cache flush, whether initiated by the

FLUSH pin or WBINVD instruction. After completion of

the snoop, and write-back, if needed, the microproces-

sor completes the copy-back of modified cache lines.

4.10 Burst Write

The Am5X86 microprocessor improves system perfor-

mance by implementing a burst write feature for cache

line write-backs and copy-backs. Standard write oper-

ations are still supported. Burst writes are always four

32-bit words and start at the beginning of a cache line

address of 0 for the starting access. The timing of the

BLAST and BRDY signals is identical to the burst read.

Figure 16 shows a burst write access. (See Figure 17

and Figure 18 for burst read and burst write access with

BOFF asserted.) In addition to using BLAST, the

CACHE signal indicates burstable cycles.

CACHE is a cycle definition pin used when in Write-back

mode (CACHE floats in Write-through mode). For pro-

cessor-initiated cycles, the signal indicates:

For a read cycle, the internal cacheability of the cycle

For a write cycle, a burst write-back or copy-back, if

KEN is asserted (for linefills).

Table 8. FLUSH Special Bus Cycles

A32–A2

M/IO D/C W/R BE3 BE2 BE1 BE0 Bus Cycle

0000 0001h

First Flush

Acknowledge

0000 0001h

Second

Flush

Acknowledge

W/R

BRDY

ADS

BLAST

ADR

M/IO

XX4

Data

XX0

XX4

XX8

XXC

Figure 16. Burst Write

CLK

CACHE

XXC

XX8

Data

to CPU

BRDY

BOFF

XX0

XX4

don’t care

ADR

XX0

ADS

BLAST

M/IO

W/R

CLK

XX4

XX8

XXC

XX4

XX8

XXC

Figure 17. Burst Read with BOFF Assertion

CACHE

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