FT810Q-R datasheet(28/63 Pages) BRIDGETEK

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FT81X Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000002 Clearance No.: BRT#004

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Table 4-12 REG_SWIZZLE RGB Pins Mapping

REG_HCYCLE, REG_HSIZE, REG_HOFFSET, REG_HSYNC0 and REG_HSYNC1 define the LCD horizontal

timings. Each register has 12 bits to allow programmable range of 0-4095 PCLK cycles. REG_VCYCLE,

REG_VSIZE, REG_VOFFSET, REG_VSYNC0 and REG_VSYNC1 define the LCD vertical timings. Each

Display

Parameter

Description

REG_HCYCLE

Total length of line (visible and non-visible) (in PCLKs)

REG_HSIZE

THD

Length of visible part of line (in PCLKs)

REG_HOFFSET

THF + THP + THB

Length of non-visible part of line (in PCLK cycles)

REG_HSYNC0

THF

Horizontal Front Porch (in PCLK cycles)

REG_HSYNC1

THF + THP

Horizontal Front Porch plus Hsync Pulse width (in PCLK

cycles)

REG_VCYCLE

Total number of lines (visible and non-visible) (in lines)

REG_VSIZE

TVD

Number of visible lines (in lines)

REG_VOFFSET

TVF + TVP + TVB

Number of non-visible lines (in lines)

REG_VSYNC0

TVF

Vertical Front Porch (in lines)

REG_VSYNC1

TVF + TVP

Vertical Front Porch plus Vsync Pulse width (in lines)

Table 4-13 Registers for RGB horizontal and vertical timings

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