MCT8317A datasheet(63/161 Pages) TI1

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8.3.19.12 Motor Lock Detection

The MCT8317A provides different lock detect mechanisms to determine if the motor is in a locked state. Multiple

detection mechanisms work together to ensure the lock condition is detected quickly and reliably. In addition to

detecting if there is a locked motor condition, the MCT8317A can also identify and take action if there is no motor

connected to the system. Each of the lock detect mechanisms and the no-motor detection can be disabled by

their respective register bits (LOCK1/2/3_EN).

8.3.19.12.1 Lock 1: Abnormal Speed (ABN_SPEED)

MCT8317A monitors the speed continuously and at any time the speed exceeds LOCK_ABN_SPEED, an

ABN_SPEED lock event is recognized and action is taken according to the MTR_LCK_MODE.

threshold is set through the LOCK_ABN_SPEED register. ABN_SPEED lock can be enabled/disabled by

LOCK1_EN.

8.3.19.12.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)

The motor is commutated by detecting the zero crossing on the phase which is in Hi-Z state. If the motor is

locked, the back-EMF will disappear and MCT8317A will be not able to detect the zero crossing. If MCT8317A

is not able to detect zero crossing for LOSS_SYNC_TIMES number of times, LOSS_OF_SYNC event is

recognized and action is taken according to the MTR_LCK_MODE. LOSS_OF_SYNC lock can be enabled/

disabled by LOCK2_EN.

8.3.19.12.3 Lock3: No-Motor Fault (NO_MTR)

The MCT8317A continuously monitors the relevant phase current (low-side phase in the present phase pattern);

if the relevant phase current stays below NO_MTR_THR for a time longer than NO_MTR_DEG_TIME, a

NO_MTR event is recognized. The response to the NO_MTR event is configured through MTR_LCK_MODE .

NO_MTR lock can be enabled/disabled by LOCK3_EN.

8.3.19.13 IPD Faults

The MCT8317A uses 12-bit timers to estimate the time during the current ramp up and ramp down during IPD,

when the motor start-up is configured as IPD (MTR_STARTUP is set to 10b). During IPD, the algorithm checks

for a successful current ramp-up to IPD_CURR_THR, starting with an IPD clock of 10MHz; if unsuccessful

(timer overflow before current reaches IPD_CURR_THR), IPD is repeated with lower frequency clocks of 1MHz,

100kHz, and 10kHz sequentially. If the IPD timer overflows (current does not reach IPD_CURR_THR) with

all the four clock frequencies, then the IPD_T1_FAULT gets triggered. Similarly the algorithm check sfor a

successful current decay to zero during IPD current ramp down using all the mentioned IPD clock frequencies. If

the IPD timer overflows (current does not ramp down to zero) in all the four attempts, then the IPD_T2_FAULT

gets triggered.

IPD gives incorrect results if the next IPD pulse is commanded before the complete decay of current due to

present IPD pulse. The MCT8317A can generate a fault called IPD_FREQ_FAULT during such a scenario . The

IPD_FREQ_FAULT maybe triggerd if the IPD frequency is too high for the IPD current limit and the IPD release

mode or if the motor inductance is too high for the IPD frequency, IPD current limit and IPD release mode.

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MCT8317A

SLLSFQ2 – JANUARY 2023

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