ST25DV64K datasheet(141/197 Pages) STMICROELECTRONICS

141 / 197 page

Test conditions specified in Table 243

Symbol

Alt.

Parameter

Min.

Max.

Unit

tSTART_OUT

I²C timeout on Start condition(1)

tXH1XH2

Input signal rise time(1)

(4)

tXL1XL2

Input signal fall time(1)

(4)

tDL1DL2

SDA (out) fall time(1)

120

tDXCX

tSU:DAT

Data in set up time(1)

tCLDX

tHD:DAT

Data in hold time(1)

tCLQX(5)

tDH

Data out hold time

100

tCLQV(6)

tAA

Clock low to next data valid (access time)

450

tCHDX(7)

tSU:STA

Start condition set up time

250

tDLCL

tHD:STA

Start condition hold time

0.25

35000(8)

µs

tCHDH

tSU:STO

Stop condition set up time

250

tDHDL

tBUF

Time between Stop condition and next Start

condition

500

I²C write time (9)

5.5

tbootDC

RF OFF and LPD = 0(1)

0.6

tbootLPD

RF OFF(1)

0.6

1. Evaluated by characterization, not tested in production.

2. tCHCL timeout.

3. tCLCH timeout.

4. There are no min. or max. values for the input signal rise and fall times. The I2C specification recommends that they are less than 120 ns

when fC < 1 MHz.

5. To avoid spurious Start and Stop conditions, a minimum delay is put between SCL = 1 and the falling or rising edge of SDA.

6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8 VCC in a compatible way with the I2C specification

(tSU:DAT (min) = 100 ns), assuming that the Rbus × Cbus time constant is less than 150 ns (as specified in Figure 76 ).

7. For a restart condition, or following a write cycle.

8. tDLCL timeout.

9. I2C write time for 1, 2, 3, or 4 bytes in EEPROM (user memory and system configuration), provided they are all located in the same page,

that is, the most significant memory address bits (b16-b2) are the same.

ST25DV04K ST25DV16K ST25DV64K

I2C parameters

DS10925 - Rev 11

page 141/197

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