000-005NT026-101

Page 5 of 9

SLG5NT026

Delay Time and Slew Rates

The two components of controlling the application of FET source voltage to the load are a fixed time delay before beginning turn

on of the FET (DLY_t below) and the Slew Time of the source voltage (Slew_t below). The Delay Time before gate voltage to the

FET is applied and the corresponding delay is 250

µs independent of FET drain voltage, source voltage or SLG5NT026 supply

voltage.

Having control over the Slew Rate of the FET’s source voltage as the FET is turning on is important in controlling dv/dt caused

transients. A power FET, for example, switching a 5 V rail which has a total of 500

µF of decoupling, fully on in 10 µs will generate

a 250 A current surge which is very undesirable. If the FET turn on time can be stretched to 1ms, the current surge to charge the

decoupling capacitors is reduced to 2.5 A. The SLG5NT026 controls slew rate of a FET’s source voltage as it is turned on. A

range of slew rates are available as device order options. Obviously the time to fully slew the source voltage to fully on is a

function of the drain supply voltage. The table and graph below shows source voltage ramp times for various slew rates supported

by the SLG5NT026 for a range of specific source voltages.

* The minimum time that ON can be de-asserted between switching cycles is 100

µs.

Slew Rates

(V/ms)

Ramp Times (ms) vs. Source Voltages (V)

1.1 V

1.5 V

1.8 V

3.3 V

5.0 V

12 V

18.5 V

4.00

0.28

0.38

0.45

0.83

1.25

3.00

4.63

2.00

0.56

0.76

0.90

1.66

2.50

6.00

9.26

6

8

10

Ramp Times (ms) vs. Source Voltage for Various Slew Rates (v/ms)

4.00

2.00

0

2

4

6

8

10

1

2

3

4

5

6

7

Source Voltage

Ramp Times (ms) vs. Source Voltage for Various Slew Rates (v/ms)

4.00

2.00

0

2

4

6

8

10

1

2

3

4

5

6

7

Source Voltage

Ramp Times (ms) vs. Source Voltage for Various Slew Rates (v/ms)

4.00

2.00