000-005NT026-101

Page 2 of 9

SLG5NT026

Pin Description

Overview

The SLG5NT026 N-Channel FET Gate Driver is used for controlling a delayed turn on and ramping slew rate of the source voltage

on N-Channel FET switches from a CMOS logic level input. Intended as a supporting control element for switched voltage rails

in energy efficient, advanced power management systems, the SLG5NT026 also integrates circuits to discharge opened switched

voltage rails. The gate driver is available in a variety of configurations supporting a range of turn-on slew rates from 0.80 V/ms

up to 4 V/ms which, depending on load supplying source voltages in the range of 1.0 V to 20 V results in ramp times from 200

µs to over 20 ms (see Application Section). Delays until the ramp begins are source voltage independent and range from 250 µs

to 5ms. A power good condition is output to indicate that the ramp-up slew of the source voltage is finished. Additionally, an

internal discharge circuit provides a controlled path to remove charge from open power rails. The SLG5NT026 gate drive is

packaged in an 8 pin DFN package.

When used with external N-Channel FETs, the SLG5NT026 supports low transient, energy efficient switching of high current loads

at source voltages ranging from 1.0 V to 20 V.

Configuration Options

Pin #

Pin Name

Type

Pin Description

1

VCC

Power

Supply Voltage

2

ON

Input

CMOS Logic Level. High True

3

NC

--

No Connect.

4

GND

GND

Ground.

5

D1

Input

FET1 Drain Connection

6

D2

Input

FET2 Drain Connection

7

G

Output

FET Gate Drive

8

PG

Output

Output Open Drain - Power Good, indicates external FET fully on.

Pull-up resistor greater than 300k

Ω recommended.

Ordering Information

Part Number

Type

SLG5NT026-xxxxxxV

TDFN-8

SLG5NT026-xxxxxxVTR

TDFN-8 - Tape and Reel (3k units)

Code (xxxxxx)

Ramp Rate (V/ms)

Delay (ms)

Discharge (

Ω)

200300

2.0

0.25

Open