CS5166 datasheet(15/25 Pages) ONSEMI

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CS5166

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Figure 23. Circuit To Implement A Dedicated OVP

Output Using The CS5166

CS5166

PWRGD

+5.0 V

10 k

2N3906

2N3904

20 k

5.0 k

+5.0 V

10 k

10 K

OVP

2N3906

56 k

15 k

VCORE

Power Good Circuit

The Power Good pin (pin 13) is an open−collector signal

consistent with TTL DC specifications. It is externally

pulled−up, and is pulled low (below 0.3 V) when the

regulator output voltage typically exceeds ± 8.5% of the

nominal output voltage. Maximum output voltage deviation

before Power Good is pulled low is ± 12%.

Figure 24. PWRGD Signal Becomes Logic High as

VOUT Enters −8.5% of Lower PWRGD Threshold,

VOUT = +2.825 V (DAC = 10111)

Trace 4− VOUT (1.0 V/div.)

Trace 2− PWRGD (2.0 V/div.)

Figure 25. Power Good Response to an Out of

Regulation Condition

Trace 4− VFB (1.0 V/div.)

Trace 2− PWRGD (2.0 V/div.)

Figure 25 shows the relationship between the regulated

output voltage VFB and the Power Good signal. To prevent

Power Good from interrupting the CPU unnecessarily, the

CS5166 has a built−in delay to prevent noise at the VFB pin

from toggling Power Good. The internal time delay is

designed to take about 75 μs for Power Good to go low and

65 μs for it to recover. This allows the Power Good signal to

be completely insensitive to out of regulation conditions that

are present for a duration less than the built in delay (see

Figure 26).

It is therefore required that the output voltage attains an out

of regulation or in regulation level for at least the built−in delay

time duration before the Power Good signal can change state.

Figure 26. Power Good is Insensitive to Out of

Regulation Conditions that are Present for a

Duration Less Than the Built In Delay

Trace 4− VFB (1.0 V/div.)

Trace 2− PWRGD (2.0 V/div.)

External Output Enable Circuit

On/off control of the regulator can be implemented

through the addition of two additional discrete components

(see Figure ). This circuit operates by pulling the Soft Start

pin high, and the ISENSE pin low, emulating a current limit

condition.

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