WM8214SCDSSLASHR datasheet(19/36 Pages) WOLFSON

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Production Data

WM8214

PD Rev 4.1 March 2007

Figure 15 ADC Input Black Level Adjust Settings

OVERALL SIGNAL FLOW SUMMARY

Figure 16 represents the processing of the video signal through the WM8214.

RESET

VRLC

CDS = 1

CDS = 0

CDACPD=1

260mV*(DAC[7:0]-127.5)/127.5

analog

See parametrics for

DAC voltages.

OP[7:0]

digital

ADC BLOCK

PGA

BLOCK

OFFSET DAC

BLOCK

INPUT

SAMPLING

BLOCK

CDS, CDACPD,CDAC[3:0], DAC[7:0],

PGA[8:0], PGAFS[1:0] and INVOP are set

by programming internal control registers.

CDS=1 for CDS, 0 for non-CDS

IN is RINP or GINP or BINP

RESET is VIN sampled during reset clamp

RLC is voltage applied to VRLC/VBIAS pin

x (65535/V

FS)

if PGAFS[1:0]=11

+65535 if PGAFS[1:0]=10

+32768 if PGAFS[1:0]=0x

PGA gain

A= 0.66+PGA[8:0]x7.34/511

OUTPUT

INVERT

BLOCK

D2 = D1 if INVOP = 0

D2 = 65535-D1 if INVOP = 1

Offset

DAC

RLC

DAC

CDACPD=0

Figure 16 Overall Signal Flow

The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the

difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the

difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC,

optionally set via the RLC DAC.

The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the

black level of the input signal towards 0V, producing V2.

The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,

outputting voltage V3.

The ADC BLOCK then converts the analogue signal, V3, to a 16-bit unsigned digital output, D1.

The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.

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