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WM8214SCDS/R Scheda tecnica(PDF) 25 Page - Wolfson Microelectronics plc

Il numero della parte WM8214SCDS/R
Spiegazioni elettronici  40MSPS 16-bit CCD Digitiser
PDF  36 Pages
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Produttore elettronici  WOLFSON [Wolfson Microelectronics plc]
Homepage  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8214SCDS/R Scheda tecnica(HTML) 25 Page - Wolfson Microelectronics plc

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Production Data
WM8214
w
PD Rev 4.1 March 2007
25
LEGACY MODE INFORMATION
The WM8214 has been designed to have a high degree of compatibility with previous generations of
Wolfson AFEs. By setting the LEGACY register bit the input timing is made compatible with the
WM819x and WM815x series of devices. Additional features such as the VSMP detect mode are
also retained in LEGACY mode.
LEGACY: PROGRAMMABLE VSMP DETECT CIRCUIT
The VSMP input is used to determine the sampling point and frequency of the WM8214. Under
normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling
frequency (as shown in the LEGACY Mode Timing Diagrams) and the input sample will be taken on
the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal
may not be readily available. The programmable VSMP detect circuit in the WM8214 allows the
sampling point to be derived from any signal of the correct frequency, such as a CCD shift register
clock, when applied to the VSMP pin.
When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge
(determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse,
INTVSMP. When POSNNEG = 1, a positive edge transition is detected and when POSNNEG = 0, a
falling edge transition is detected. INTVSMP can optionally be delayed by a number of MCLK
periods, specified by the VDEL[2:0] bits. Figure 20 shows the internal VSMP pulses that can be
generated by this circuit for a typical clock input signal. The internal VSMP pulse is then applied to
the timing control block in place of the normal VSMP pulse provided from the input pin.
The sampling point occurs on the first rising MCLK edge after this internal VSMP pulse, as shown in
the LEGACY Mode Timing Diagrams.
MCLK
VSMP
(VDEL = 000) INTVSMP
POSNNEG = 1
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP
POSNNEG = 0
(VDEL = 000) INTVSMP
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP
INPUT
PINS
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Figure 20 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit



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