P83CE558EBBSLASHYYY datasheet(20/72 Pages) PHILIPS

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Philips Semiconductors

Preliminary specification

P83CE558/P80CE558/P89CE558

Single-chip 8-bit microcontroller

1996 Aug 06

Digital Input Port Register P5

Port 5 Special Function Register P5 always represents the binary

value of the logic level at input pins P5.0/ADC0...P5.7/ADC7. P5 is

not affected by chip reset. P5 is a read only register. Its hardware

address is C7H. P5 is not bit addressable.

Reading Special Function Register P5 does not affect A/D

conversions. But it is recommended to use the digital input port

function of the hardware Port 5 only as an alternative to analog input

voltage conversions. Simultaneous mixed operation is discouraged

for the sake of A/D conversion result reliability and accuracy.

For further information on Port 5, refer to the “I/O facilities” section.

For further information on A/D Special Function Registers, refer to

the “Internal Data Memory” section.

P5 (C7H)

P5.7

P5.6

P5.5

P5.4

P5.3

P5.2

P5.1

P5.0

Figure 18. Digital input port register P5.

Reset

After a RESET of the microcontroller the ADCON and ADPSS

are not initialized by a RESET.

Idle and Power-down Mode

The A/D Converter is active only when the microcontroller is in

normal operating mode. If the Idle or Power-down Mode is activated,

then the ADC is switched off and put into a power saving idle state –

a conversion in progress is aborted, a previously set ADSST flag is

cleared and the internal clock is halted. The conversion result

registers are not affected.

The interrupt flag ADINT will not be set by activation of Idle or

Power-down Mode. A previously set flag ADINT will not be cleared

by the hardware. (Note: ADINT cannot be cleared by hardware at

all, except for a RESET – it must be cleared by the user software.)

After a wakeup from Idle or Power-down Mode a set flag ADINT

indicates that at least one autoscan loop was finished completely

before the microcontroller was put into the respective power

reduction mode and it indicates that the stored result data may be

fetched now – if desired.

For further information on Idle and Power-down Mode, refer to the

“Power reduction modes” section.

Timing

A programmable prescaler is controlled by the bits ADPR1 and

ADPR0 in register ADCON to adapt the conversion time for different

microcontroller clock frequencies.

Table 11 shows conversion times (tconv) for one A/D conversion at

some convenient system clock frequencies (fclk) and ADC prescaler

divisors (m), which are user selectable by the bits ADCON.7/ADPR1

and ADCON.6/ADPR0.

For conversion times outside the limits for tconv the specified ADC

characteristics are not guaranteed; (prohibited conversion times are

put in brackets):

Table 11.

Conversion time configuration

examples (tconv/

µs)

fCLK

6 MHz

8 MHz

12 MHz

16 MHz

[74]

[98]

19.5

37.5

[55.5]

[73.5]

[13]

[9.75]

18.75

27.75

36.75

Conversion time tconv = (6 m + 1) machine cycles

A conversion time tconv consists of one sample time period (which

equals two bit conversion times), 10 bit conversion time periods and

one machine cycle to store the result.

After result storage an extra initializing time period follows to select

the next analog input channel (according to the contents of SFR

ADPSS), before the input signal is sampled.

Thus the time period between two adjacent conversions within an

autoscan loop is larger than the pure time tconv. This autoscan cycle

time is ( 7 m ) machine cycles.

At the start of an autoscan conversion the time between writing to

SFR ADCON and the first analog input signal sampling depends on

the current prescaler value (m) and the relative time offset between

this write operation and the internal (divided) ADC clock. This gives

a variation range for the A/D conversion start time of ( m / 2 )

machine cycles.

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