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AVR32AP Scheda tecnica(PDF) 1 Page - ATMEL Corporation |
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AVR32AP Scheda tecnica(HTML) 1 Page - ATMEL Corporation |
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1 / 181 page ![]() Feature Summary • 32-bit load/store AVR32B RISC architecture • 15 general-purpose 32-bit registers • 32-bit Stack Pointer, Program Counter and Link Register reside in register file • Fully orthogonal instruction set • Pipelined architecture allows one instruction per clock cycle for most instructions • Byte, half-word, word and double word memory access • Shadowed interrupt context for INT3 and multiple interrupt priority levels • Privileged and unprivileged modes enabling efficient and secure Operating Systems • Full MMU allows for operating systems with memory protection • Instruction and data caches • Innovative instruction set together with variable instruction length ensuring industry leading code density • DSP extention with saturating arithmetic, and a wide variety of multiply instructions • SIMD extention for media applications • Dynamic branch prediction and return address stack for fast change-of-flow • Powerful On-Chip Debug system • Coprocessor interface 32001A–AVR32–06/06 32-bit AVR® Microcontroller AVR32 AP Technical Reference Manual |
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