AVR32AP datasheet(49/181 Pages) ATMEL

49 / 181 page

32001A–AVR32–06/06

AVR32

The U0 segment is accessible in the unprivileged user mode. This segment is cacheable and

translated, depending upon the configuration of the cache and the memory management unit. If

accesses to other memory addresses than the ones within U0 is made in application mode, an

access error exception is issued.

The virtual address map is summarized in Table 4-1.

The segment translation can be disabled by clearing the S bit in the MMUCR. This will place all

the virtual memory space into a single 4 GB mapped memory space. Segment translation is

enabled by default.

The AVR32 architecture has two translations of addresses.

Segment translation (enabled by the MMUCR[S] bit)

Page translation (enabled by the MMUCR[E] bit)

Both these translations are performed by the MMU and they can be applied independent of each

other. This means that you can enable:

No translation. Virtual and physical addresses are the same.

Segment translation only. The virtual and physical addresses are the same for

addresses residing in the P0, P4 and U0 segments. P1, P2 and P3 are mapped to the

physical address range 0x00000000 to 0x1FFFFFFF.

Page translation only. All addresses are mapped as described by the TLB entries.

Doing this will give all access permission control to the AP bits in the TLB entry match-

ing the virtual address, and allow all virtual addresses to be translated.

Both segment and page translations. P1 and P2 are mapped to the physical address

range 0x00000000 to 0x1FFFFFFF. U0, P0 and P3 are mapped as described by the

TLB entries. The virtual and physical addresses are the same for addresses residing in

the P4 segment.

The segment translation is by default turned on and the page translation is by default turned off

after reset. The segment translation is summarized in Figure 4-2 on page 50.

Table 4-1.

The virtual address map

Virtual

address

[31:29]

Segment

name

Virtual

Address Range

Segment

size

Accessible

from

Default

segment

translated

Characteristics

111

0xFFFF_FFFF to

0xE000_0000

512 Mb

Privileged

System space

Unmapped, Uncacheable

110

0xDFFF_FFFF to

0xC000_0000

512 Mb

Privileged

Yes

Mapped,

Cacheable

101

0xBFFF_FFFF to

0xA000_0000

512 Mb

Privileged

Yes

Unmapped, Uncacheable

100

0x9FFF_FFFF to

0x8000_0000

512 Mb

Privileged

Yes

Unmapped, Cacheable

0xx

P0 / U0

0x7FFF_FFFF to

0x0000_0000

2 Gb

Unprivileged

Privileged

Mapped, Cacheable

AVR32AP Scheda tecnica(PDF) 49 Page - ATMEL Corporation

AVR32AP Scheda tecnica(HTML) 49 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL