TMD3702VC datasheet(20/57 Pages) OSRAM

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Datasheet, Public

Page 19

[v2-00] 2023-Mar-14

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TMD3702VC − Register Description

ATIME Register (Address 0x81)

Figure 22:

ATIME Register

The ATIME register controls the integration time of the ALS

ADCs. The timer is implemented with a down counter with 0x00

as the terminal count. The timer is clocked at a 2.78ms nominal

rate. Loading 0x00 will generate a 2.78ms integration time,

loading 0x01 will generate a 5.56ms integration time, and so

forth.

PRATE Register (Address 0x82)

Figure 23:

PRATE Register

Addr:0x81

ATIME

Bit

Bit Name

Default

Access

Bit Description

7:0

ATIME

0x00

ALS/Color value that specifies the integration time in

2.78ms intervals. 0x00 indicates 2.78ms. The maximum

ALS value depends on the integration time. For every

2.78ms, the maximum value increases by 1024. This

means that to be able to reach ALS full scale, the

integration time has to be at least 64*2.78ms.

Value

Integration

Cycles

Integration

Time

Maximum

ALS Value

0x00

2.78ms

1023

0x01

5.56ms

2047

0x11

50.0ms

18431

0x23

100ms

36863

0x3F

178ms

65535

0xFF

256

712ms

65535

Addr:0x82

PRATE

Bit

Bit Name

Default

Access

Bit Description

7:0

PRATE

0x1F

This register defines the duration of 1 Prox Sample,

which is (PRATE + 1)*88μs.

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