TMD3702VC datasheet(27/57 Pages) OSRAM

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[v2-00] 2023-Mar-14

TMD3702VC − Register Description

The frequency of consecutive Clear (C) channel results outside

of threshold limits are counted; this count value is compared

against the APERS value. If the counter is equal to the APERS

setting an interrupt is asserted. Any time a Clear (C) channel

result is inside the threshold values the counter is cleared.

CFG0 Register (Address 0x8D)

Figure 34:

CFG0 Register

PCFG0 Register (Address 0x8E)

Figure 35:

PCFG0 Register

Addr: 0x8D

CFG0

Bit

Bit Name

Default

Access

Bit Description

7:3

Reserved

01000

Reserved. Must be set to default value.

2WLONG

When WLONG (Wait Long) is asserted the wait period

as set by WTIME is increased by a factor of 12.

Reserved

Reserved. Must be set to default value.

PPULSE_

LEN_16x

0RW

When PPULSE_LEN_16X is asserted, the proximity

pulse length is extended by a factor of 16. See the

PPULSE_LEN bit description in the PCFG0 register.

Addr: 0x8E

PCFG0

Bit

Bit Name

Default

Access

Bit Description

7:6

PPULSE_LEN

(01)

Proximity pulse length. The pulse length can be

extended by a factor of 16x with the assertion of the

PPULSE_LEN_16x bit in CFG0.

Value

Pulse Length

0 (00)

4μs / 64μs

1 (01)

8μs / 128μs

2 (10)

16μs / 256μs

3 (11)

32μs / 512μs

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