TMD3702VC datasheet(24/57 Pages) OSRAM

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Datasheet, Public

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[v2-00] 2023-Mar-14

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TMD3702VC − Register Description

PILTL Register (Address 0x88)

Figure 29:

PILTL Register

PILTH Register (Address 0x89)

Figure 30:

PILTH Register

The contents of the PILTH and PILTL registers are combined and

treated as a fourteen (14) bit threshold low value. If the value

generated by the proximity ADC (PDATA) is below the PILTL/H

threshold and the PPERS value is reached, the PINT bit is

asserted. If PIEN is set, then the INT pin will also assert. When

setting the 14-bit proximity threshold, PILTL must be written

first, immediately follow by PILTH. Internally, the lower 8-bits

are buffered until the upper 8-bits are written. As the upper

8-bits are written both the high and low bytes are

simultaneously latched as a 14-bit value.

If Automatic Pulse Control (APC) is disabled by setting bit 6 in

CFG6 to 1, then the proximity data converts to a 10-bit value.

PILTL contains a 8-bit threshold which is compared against the

upper 8-bits of the 10-bit value. PILTH is ignored.

Addr: 0x88

PILTL

Bit

Bit Name

Default

Access

Bit Description

7:0

PILTL

0x00

This register contains the low byte of the 14-bit

proximity LOW threshold when APC is enabled. If APC

is disabled, this register contains the LOW threshold

which is an 8-bit value which is compared against the

upper 8-bits of the 10-bit proximity value.

Addr: 0x89

PILTH

Bit

Bit Name

Default

Access

Bit Description

7:6

Reserved

Reserved. Must be set to default value.

5:0

PILTH

0x00

This register contains the upper 6 bits of the 14-bit

proximity LOW threshold when APC is enabled. If APC

is disabled, this register is ignored.

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