M48Z08 datasheet(6/16 Pages) STMICROELECTRONICS

Il numero della parte	M48Z08

Spiegazioni elettronici	5V, 64 Kbit (8Kb x 8) ZEROPOWER® SRAM

PDF	16 Pages

Scroll/Zoom	100%

Produttore elettronici	STMICROELECTRONICS [STMicroelectronics]

Homepage	http://www.st.com

Logo

6 / 16 page

M48Z08, M48Z18

6/16

WRITE Mode

The M48Z08/18 is in the WRITE Mode whenever

W and E are active. The start of a WRITE is refer-

enced from the latter occurring falling edge of W or

A WRITE is terminated by the earlier rising edge of

W or E. The addresses must be held valid through-

out the cycle. E or W must return high for a mini-

mum of tEHAX from Chip Enable or tWHAX from

WRITE Enable prior to the initiation of another

READ or WRITE cycle. Data-in must be valid tD-

VWH prior to the end of WRITE and remain valid for

tWHDX afterward. G should be kept high during

WRITE cycles to avoid bus contention; although, if

the output bus has been activated by a low on E

and G, a low on W will disable the outputs tWLQZ

after W falls.

Figure 6. WRITE Enable Controlled, WRITE Mode AC Waveform

Figure 7. Chip Enable Controlled, WRITE Mode AC Waveforms

AI01386

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A12

DQ0-DQ7

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

AI01387B

tAVAV

tEHAX

tDVEH

A0-A12

DQ0-DQ7

VALID

tAVEH

tAVEL

tAVWL

tELEH

tEHDX

DATA INPUT

M48Z08 Scheda tecnica(PDF) 6 Page - STMicroelectronics

M48Z08 Scheda tecnica(HTML) 6 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Scheda tecnica Scarica

Link URL