M48Z08 datasheet(5/16 Pages) STMICROELECTRONICS

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M48Z08, M48Z18

READ Mode

The M48Z08/18 is in the READ Mode whenever W

(WRITE Enable) is high and E (Chip Enable) is

low. The device architecture allows ripple-through

access of data from eight of 65,536 locations in the

static storage array. Thus, the unique address

specified by the 13 address inputs defines which

one of the 8,192 bytes of data is to be accessed.

Valid data will be available at the Data I/O pins

within address access time (tAVQV) after the last

address input signal is stable, providing that the E

and G access times are also satisfied. If the E and

G access times are not met, valid data will be

available after the latter of the Chip Enable Access

time (tELQV) or Output Enable Access time

(tGLQV).

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

ed before tAVQV, the data lines will be driven to an

indeterminate state until tAVQV. If the address in-

puts are changed while E and G remain active,

output data will remain valid for Output Data Hold

time (tAXQX) but will go indeterminate until the next

address access.

Figure 5. READ Mode AC Waveforms

Note: WRITE Enable (W) = High.

Table 3. READ Mode AC Characteristics

Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).

2. CL = 30pF.

Symbol

Parameter(1)

M48Z08/M48Z18

Unit

Min

Max

tAVAV

READ Cycle Time

100

tAVQV

Address Valid to Output Valid

100

tELQV

Chip Enable Low to Output Valid

100

tGLQV

Output Enable Low to Output Valid

tELQX

(2)

Chip Enable Low to Output Transition

tGLQX

(2)

Output Enable Low to Output Transition

tEHQZ

(2)

Chip Enable High to Output Hi-Z

tGHQZ

(2)

Output Enable High to Output Hi-Z

tAXQX

Address Transition to Output Transition

AI01385

tAVAV

tAVQV

tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

VALID

A0-A12

DQ0-DQ7

VALID

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