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M48Z08 Scheda tecnica(PDF) 4 Page - STMicroelectronics |
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M48Z08 Scheda tecnica(HTML) 4 Page - STMicroelectronics |
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4 / 16 page ![]() M48Z08, M48Z18 4/16 Figure 4. Block Diagram OPERATION MODES The M48Z08/18 also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condi- tion. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls be- low approximately 3V, the control circuitry con- nects the battery which maintains data until valid power returns. Table 2. Operating Modes Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10., page 12 for details. AI01394 LITHIUM CELL VPFD VCC VSS VOLTAGE SENSE AND SWITCHING CIRCUITRY 8K x 8 SRAM ARRAY A0-A12 DQ0-DQ7 E W G POWER Mode VCC E G W DQ0-DQ7 Power Deselect 4.75 to 5.5V or 4.5 to 5.5V VIH X X High Z Standby WRITE VIL X VIL DIN Active READ VIL VIL VIH DOUT Active READ VIL VIH VIH High Z Active Deselect VSO to VPFD(min) (1) X X X High Z CMOS Standby Deselect ≤ VSO(1) X X X High Z Battery Back-up Mode |
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