ADL5309ACBZ-R7 datasheet(17/25 Pages) AD

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Data Sheet

ADL5309

APPLICATIONS INFORMATION

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Rev. 0 | 17 of 25

INP1 AND INP2 INTERFACES

The photocurrent input, from the anode of the photodiode, flows

into the INP pin. The maximum operating input current is 25 mA.

Figure 43. Simplified Input Interface

OUT1 AND OUT2 INTERFACES

The logarithmic VOUTchanges logarithmically with the current ap-

plied to INP. The nominal slope is 200 mV/dec in the range of

100 pA to 25 mA of the current input over the entire operating

temperature.

Figure 44. Simplified Output Interface

PDB1 AND PDB2 INTERFACES

The PDB interface pin is shown in Figure 45. The purpose of this

pin is to generate a bias voltage to be used with photodiodes.

In an optical system, the photodiode produces an output current

proportional to the optical input power. This results in an output

dynamic range that is twice (in dB) the optical input power dynamic

range and can be high. At low input power, the input current

can be small (on the order of pA). With an IIN it is necessary to

minimize the dark current leakage of the photodiode by keeping the

voltage drop across the diode as small as possible. At higher input

powers, the photodiode current can be relatively large (up to 10s of

mA). This photocurrent, impressed on the internal series resistance

of the diode, results in an increasing voltage drop for increasing

optical power.

To address the dark current issue, the ADL5309 provides a photo-

diode bias that keeps the cathode-to-anode voltage of the photo-

diode close to zero for low input current, therefore reducing any

dark currents. For higher current operation, the photodiode bias

interface tracks the input current and produces an output voltage

directly proportional to the input current,with the gain adjustable by

using the PDBG register. The RT can be disabled by asserting the

PDBG_FIX bit or setting PDBG = 0. The photodiode bias VOUT is

limited by the VCC.

Figure 45. Simplified Photodiode Bias Interface

SUM INTERFACE

A large voltage difference between nodes can cause a significant

leakage current, even if the impedance between the nodes is

relatively high. Guarding reduces the errors due to leakages. The

concept of guarding is to surround the high-impedance conductor

with another conductor (guard) driven to the same voltage potential.

If there is no voltage across the insulation resistance (between

the high-impedance conductor and guard), there can be no current

flowing through it.

Reducing errors from external sources in a current-sensing circuit

requires a different approach than the voltage sensing input of the

typical high-impedance op amp circuit. Leakage can be a significant

source of error for highly sensitive logarithmic amplifiers (log amps),

especially at the low end of amplifier's range. For example, a 1 GΩ

leakage path to the ground from the current line INP with SUM set

to the default 1.6 V generates a 1.6 nA offset.

The ADL5309 uses the SUM node as guard pins that shield the

input current lines INP. The SUM node has an internal 500 Ω

resistor connected to a 1.6 V voltage reference buffer.

Figure 46. Simplified SUM Interface

ADCREF INTERFACE

The input current measurement accuracy using the internal ADC

as illustrated in Figure 5 and Figure 8 can be improved by

applying a stable reference voltage to the ADCREF pin. This

reference voltage can be sampled by the ADC by setting registers

ADCREF_PIN_SEL (0x0A) = 0x2C, ADC_MUX_CTRL (0x04) =

0x08 and ADCREF_MUX_SEL (0x07) = 0x03. An ideal ADC value

is calculated by the following equation:

ADCREF

_value_ideal=VADCREF×16383

2.2

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