Data Sheet

ADL5309

SERIAL PORT INTERFACE

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Rev. 0 | 22 of 25

SHADOW REGISTERS

The shadow registers enable detailed configuration of the adaptive

photodiode bias circuits in both channels, enabling more advanced

features than the default settings provide. Access to these registers

is provided through an indirect addressing method using the shad-

ow access registers (see the Shadow Access Registers section).

Table 9 summarizes the available registers. For a detailed explana-

tion of available photodiode bias configuration see the Photodiode

Bias section. By default, the shadow registers are locked and

accessible for read only. To unlock the registers and obtain write

access, first write 0xE5 to SREG_20 (using indirect addressing).

The unlocked state will remain in effect until these are locked again

by writing 0x00 to SREG_20, or a (soft) reset is issued.

Table 9. ADL5309 Shadow Register Details

Address Name

Bits

Field Name

Description

Default

Access

0x07

SREG_07

6

PDBG_FIX

Photodiode bias transresistance is disabled (effectively set to zero) if this bit is set,

making the photodiode bias voltage constant vs. input current.

0x00

R/W

[5:0]

PDBG

Photodiode bias transresistance control when PDBG_FIX is not set, coarse photodiode

bias voltage control when PDBG_FIX is set.

0x08

SREG_08

[7:4]

IDZ

Photodiode bias transresistance threshold control.

0x00

R/W

[3:0]

IPDB

Controls the photodiode bias voltage of both channels at zero input current in 25 mV

steps.

0x0A

SREG_0A

[7:0]

OS1

Channel 1 V_PDB - V_INP offset control in 150 μV steps.

0xXX

R/W

0x0B

SREG_0B

[7:0]

OS2

Channel 2 V_PDB - V_INP offset control in 150 μV steps.

0xXX

R/W

0x0C

SREG_0C

[7:4]

IMAX

The IMAX register (four MSBs in shadow register 0x0C) sets the maximum sourcing

current of the PDB pin. It is trimmed in the factory to about 30 mA. If the IMAX is

changed, it may affect the precision of the OS factory trims (Shadow Register 0x0A and

Shadow Register 0x0B) and is recommended to be re-calibrated.

0xXF

R/W

[3:0]

CF

Capacitor feedback. Sets low input current bandwidth.

R/W

0x20

SREG_20

[7:0]

UNLOCK

Write 0xE5 to unlock for read/write, and write 0x00 to lock shadow registers for

read-only.

0x00

R/W