Data Sheet

AD9914

REGISTER MAP AND BIT DESCRIPTIONS

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Rev. G | 46 of 48

Table 25. Bit Descriptions for Lower Frequency Jump Register

Bit(s)

Mnemonic

Description

[31:0]

Lower frequency jump point

32-bit digital lower frequency jump value. During a rising frequency sweep, when the lower frequency jump value is

reached, the output frequency jumps to the upper frequency jump value instantaneously and continues frequency

sweeping in a phase-continuous manner. During a falling frequency sweep, when the upper frequency jump value

is reached, the output frequency jumps to the lower frequency jump value instantaneously and continues frequency

sweeping in a phase-continuous manner.

Upper Frequency Jump Register—Address 0x0A

This register is effective only if the digital ramp enable bit (0x01[19]) = 1, the frequency jump enable bit (0x01[14]) = 1 in the CFR2 register, and

at least one of the no-dwell bits (CFR2[18:17]) is Logic 0. See the Digital Ramp Generator (DRG) section for details.

Table 26. Bit Descriptions for Upper Frequency Jump Register

Bit(s)

Mnemonic

Description

[31:0]

Upper frequency jump point

32-bit digital upper frequency jump value. During a rising frequency sweep, when the lower frequency jump

value is reached, the output frequency jumps to the upper frequency jump value instantaneously and continues

frequency sweeping in a phase-continuous manner. During a falling frequency sweep, when the upper frequency

jump value is reached, the output frequency jumps to the lower frequency jump value instantaneously and

continues frequency sweeping in a phase-continuous manner.

Profile Registers

There are 16 serial input/output addresses (Address 0x0B to Address 0x01A) dedicated to device profiles. Eight of the 16 profiles house up

to eight single tone frequencies. The remaining eight profiles contain the corresponding phase offset and amplitude parameters relative to the

profile pin setting.

To enable profile mode, set the profile mode enable bit in CFR2 (0x01[23]) = 1. The active profile register is selected using the external PS[2:0]

pins.

Profile 0 to Profile 7, Single Tone Registers—0x0B, 0x0D, 0x0F, 0x11, 0x13, 0x15, 0x17, 0x19

Four bytes are assigned to each register.

Table 27. Bit Descriptions for Profile 0 to Profile 7 Single Tone Registers

Bit(s)

Mnemonic

Description

[31:0]

Frequency tuning word

This 32-bit number controls the DDS frequency.

Profile 0 to Profile 7, Phase Offset and Amplitude Registers—0x0C, 0x0E, 0x10, 0x12, 0x14, 0x16,

0x18, 0x1A

Four bytes are assigned to each register.

Table 28. Bit Descriptions for Profile 0 to Profile 7 Phase Offset and Amplitude Registers

Bit(s)

Mnemonic

Description

[31:28]

Open

Open.

[27:16]

Amplitude scale factor

This 12-bit word controls the DDS amplitude. Note that the OSK enable bit (0x00[8]) must be set to logic high to make amplitude

adjustments.

[15:0]

Phase offset word

This 16-bit word controls the DDS phase offset.