Data Sheet

AD9914

TABLE OF CONTENTS

analog.com

Rev. G | 2 of 48

Features................................................................ 1

Applications........................................................... 1

Functional Block Diagram......................................1

General Description...............................................4

Specifications........................................................ 5

DC Specifications............................................... 5

AC Specifications............................................... 6

Absolute Maximum Ratings...................................9

Thermal Performance.........................................9

ESD Caution.......................................................9

Pin Configuration and Function Descriptions...... 10

Typical Performance Characteristics................... 12

Equivalent Circuits...............................................16

Theory of Operation.............................................17

Single Tone Mode.............................................17

Profile Modulation Mode...................................17

Digital Ramp Modulation Mode........................ 17

Parallel Data Port Modulation Mode.................17

Programmable Modulus Mode......................... 18

Mode Priority.................................................... 18

Functional Block Detail........................................ 20

DDS Core.........................................................20

12-Bit DAC Output............................................21

DAC Calibration Output....................................21

Reconstruction Filter........................................ 21

Clock Input (REF_CLK/REF_CLK)...................22

Output Shift Keying (OSK)............................... 23

Digital Ramp Generator (DRG)........................ 24

Power-Down Control........................................ 29

Programming and Function Pins......................... 31

Serial Programming.............................................34

Control Interface—Serial Input/Output............. 34

General Serial Input/Output Operation.............34

Instruction Byte.................................................34

Serial Input/Output Port Pin Descriptions.........34

Serial Input/Output Timing Diagrams............... 35

MSB/LSB Transfers..........................................35

Parallel Programming (8-/16-Bit)......................... 36

Register Map and Bit Descriptions...................... 37

Register Bit Descriptions.................................. 41

Outline Dimensions............................................. 48

Ordering Guide.................................................48

Evaluation Boards............................................ 48

REVISION HISTORY

6/2022—Rev. F to Rev. G

Changes to Base DDS Power, PLL Disabled Parameter and Base DDS Power, PLL Enabled

Parameter, Table 1.........................................................................................................................................5

Changes to SYNC_CLK Output Driver, Duty Cycle Parameter, Data Latency (Pipeline Delay)

Parameter, and SCLK Clock Rate (1/tCLK ) Parameter, Table 2.....................................................................6

Changes to Table 5........................................................................................................................................10

Changes to Figure 12 Caption.......................................................................................................................13

Changes to Figure 14 Caption.......................................................................................................................13

Added Figure 22; Renumbered Sequentially................................................................................................. 15

Change to Figure 23...................................................................................................................................... 15

Changes to Theory of Operation Section ......................................................................................................17

Changes to Profile Modulation Mode Section................................................................................................17

Changes to Digital Ramp Modulation Mode Section..................................................................................... 17

Changes to Parallel Data Clock (SYNC_CLK) Section..................................................................................17

Changes to Programmable Modulus Mode Section...................................................................................... 18

Changes to Reconstruction Filter Section......................................................................................................21

Changes to REF_CLK/REF_CLK Overview Section and Figure 33.............................................................. 22

Changes to Direct Driven REF_CLK/REF_CLK Section............................................................................... 22

Changes to Phase-Locked Loop (PLL) Multiplier Section............................................................................. 22

Changes to PLL Lock Indication Section....................................................................................................... 23

Changes to DRG Overview Section and Table 9........................................................................................... 24

Added Table 10; Renumbered Sequentially...................................................................................................24

Changes to DRG Slope Control Section........................................................................................................25

Changes to DRG Limit Control Section......................................................................................................... 26