4571 datasheet(56/126 Pages) RENESAS

56 / 126 page

Rev.1.02

May 25, 2007

Page 56 of 124

REJ03B0179-0102

4571 Group

(10)P20/INT0 pin

(1) Bit 3 of register I1

When the input of the P20/INT0 pin is controlled with the

bit 3 of register I1 in software, be careful about the

following notes.

• Depending on the input state of the P20/INT0 pin, the external

0 interrupt request flag (EXF0) may be set when the bit 3 of

unexpected interrupt, clear the bit 0 of register V1 to “0” (refer

to (1) in Figure 55) and then, change the bit 3 of register I1.

In addition, execute the SNZ0 instruction to clear the EXF0

flag to “0” after executing at least one instruction (refer to (2)

in Figure 55).

Also, set the NOP instruction for the case when a skip is

performed with the SNZ0 instruction (refer to (3) in Figure

55).

Fig 55. External 0 interrupt program example-1

(2) Bit 3 of register I1

When the bit 3 of register I1 is cleared to “0”, the RAM

back-up mode is selected and the input of INT0 pin is

disabled, be careful about the following notes.

• When the INT0 pin input is disabled (register I13 = “0”), set

the key-on wakeup of INT0 pin to be invalid (register L10 =

“0”) before system enters to the RAM back-up mode. (refer to

(1) in Figure 56).

Fig 56. External 0 interrupt program example-2

(3) Bit 2 of register I1

When the interrupt valid waveform of the P20/INT0 pin is

changed with the bit 2 of register I1 in software, be careful

about the following notes.

• Depending on the input state of the P20/INT0 pin, the external

1 interrupt request flag (EXF0) may be set when the bit 2 of

unexpected interrupt, clear the bit 0 of register V1 to “0” (refer

to (1) in Figure 57) and then, change the bit 2 of register I1 is

changed.

In addition, execute the SNZ0 instruction to clear the EXF0

flag to “0” after executing at least one instruction (refer to (2)

in Figure 57).

Also, set the NOP instruction for the case when a skip is

performed with the SNZ0 instruction (refer to (3) in Figure

57).

Fig 57. External 0 interrupt program example-3

•

; (

×××02)

TV1A

; The SNZ0 instruction is valid ...... (1)

; (1

×××2)

TI1A

; Control of INT0 pin input is changed

NOP

...................................................... (2)

SNZ0

; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP

...................................................... (3)

•

×: these bits are not used here.

•

; (

×××02)

TL1A

; INT0 key-on wakeup disabled .....(1)

EPOF

POF

; RAM back-up

•

×: these bits are not used here.

•

; (

×××02)

TV1A

; The SNZ0 instruction is valid ......(1)

; (1

×××2)

TI1A

; Interrupt valid waveform is changed

NOP

.......................................................(2)

SNZ0

; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP

.......................................................(3)

•

×: these bits are not used here.

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