4571 datasheet(29/126 Pages) RENESAS

29 / 126 page

Rev.1.02

May 25, 2007

Page 29 of 124

REJ03B0179-0102

4571 Group

Fig 32. Timers structure (2)

Watchdog reset

signal

reset signal

(Note 3)

DWDT instruction

WRST instruction

Reset signal

(Note 4)

(Note 2)

WRST instruction

Watchdog timer (16)

1 - - - - - - - - - - - - - 16

INSTCK

WDF1

WEF

C/CNTR1

Port C output

PWMOUT

PWMOD

W12

W51

T1UDF

W30

XIN

W31

Timer 3 (8)

Reload Register R3L (8)

(TAB3)

(T3AB)

(TAB3)

(T3R3L)

Reload control circuit

(Note 1)

Reload Register R3H (8)

(T3HAB)

W33

Timer 3

interrupt

1/2

ORCLK

W32

“H” interval expansion

T3F

PWMOD

T2UDF: Timer 2 underflow signal

ORCLK: Prescaler output

Note 1: When the CNTR1 output function is valid (W33=“1”), the value is auto-reloaded alternately from reload register

R3L and R3H every timer 3 underflow.

When the CNTR1 function is invalid (W33=“0”), the value is auto-reloaded from reload register R3L only.

2: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed

while flag WDF1 = “1”.

The WRST instruction is equivalent to the NOP instruction while flag WDF1 = “0”.

3: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and

WRST instruction are executed continuously.

4: The WEF flag is set to “1” at system reset or RAM back-up mode.

Data is set automatically from each reload register

when timer underflows (auto-reload function).

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