ADPA7002AEHZ-R7 datasheet(14/20 Pages) AD

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Data Sheet

ADPA7002

THEORY OF OPERATION

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Rev. A | 14 of 20

The architecture of the ADPA7002, a medium power amplifier,

is displayed in Figure 50. The ADPA7002 uses a cascaded, three-

stage amplifier operating in quadrature between two 90° hybrids.

A portion of the RF output signal is directionally coupled to a diode

to detect the RF output power. When the diode is dc biased, the

diode rectifies the RF power and makes the RF power available for

measurement as dc voltage at the VDET pin. Temperature compen-

sation is accomplished by referencing a symmetrical diode circuit

that is not coupled to the RF output that contains a dc voltage

output at the VREF pin. The difference of VREF − VDET provides

a temperature compensated signal that is proportional to the RF

output.

The 90° hybrids ensure that the input and output return losses are

>12 dB. See the application circuits in the Applications Information

section for further details on biasing the various blocks.

To obtain optimal performance from the ADPA7002 and to avoid

damaging the device, follow the recommended biasing sequences

described in the Biasing Procedures section.

Figure 50. Simplified Architecture of the ADPA7002

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