DSP56303 datasheet(150/292 Pages) FREESCALE

150 / 292 page

DSP56303 User’s Manual, Rev. 2

7-18

Freescale Semiconductor

Enhanced Synchronous Serial Interface (ESSI)

corresponding SC (or STD in the case of TX0) signal remains in a high-impedance state. The

CRB bits are cleared by either a hardware RESET signal or a software RESET instruction.

Table 7-4. ESSI Control Register B (CRB) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

REIE

Receive Exception Interrupt Enable

When the REIE bit is set, the DSP is interrupted when both RDF and ROE

in the ESSI status register are set. When REIE is cleared, this interrupt is

disabled. The receive interrupt is documented in

Section 7.3.3, Exceptions, on page 7-7. A read of the status register

followed by a read of the receive data register clears both ROE and the

pending interrupt.

TEIE

Transmit Exception Interrupt Enable

When the TEIE bit is set, the DSP is interrupted when both TDE and TUE in

the ESSI status register are set. When TEIE is cleared, this interrupt is

disabled. The use of the transmit interrupt is documented

in Section 7.3.3, Exceptions, on page 7-7. A read of the status register,

followed by a write to all the data registers of the enabled transmitters,

clears both TUE and the pending interrupt.

RLIE

Receive Last Slot Interrupt Enable

Enables/disables an interrupt after the last slot of a frame ends when the

ESSI is in Network mode. When RLIE is set, the DSP is interrupted after the

last slot in a frame ends regardless of the receive mask register setting.

When RLIE is cleared, the receive last slot interrupt is disabled. The use of

the receive last slot interrupt is documented in

Section 7.3.3, Exceptions, on page 7-7. RLIE is disabled when the ESSI is

in On-Demand mode (DC = $0).

TLIE

Transmit Last Slot Interrupt Enable

Enables/disables an interrupt at the beginning of the last slot of a frame

when the ESSI is in Network mode. When TLIE is set, the DSP is

interrupted at the start of the last slot in a frame regardless of the transmit

mask register setting. When TLIE is cleared, the transmit last slot interrupt

is disabled. The transmit last slot interrupt is documented

in Section 7.3.3, Exceptions, on page 7-7. TLIE is disabled when the ESSI

is in On-Demand mode (DC = $0).

RIE

Receive Interrupt Enable

Enables/disables a DSP receive data interrupt; the interrupt is generated

when both the RIE and receive data register full (RDF) bit (in the SSISR)

are set. When RIE is cleared, this interrupt is disabled. The receive interrupt

is documented in Section 7.3.3, Exceptions, on page 7-7. When the

receive data register is read, it clears RDF and the pending interrupt.

Receive interrupts with exception have higher priority than normal receive

data interrupts. If the receiver overrun error (ROE) bit is set (signaling that

an exception has occurred) and the REIE bit is set, the ESSI requests an

SSI receive data with exception interrupt from the interrupt controller.

TIE

Transmit Interrupt Enable

Enables/disables a DSP transmit interrupt; the interrupt is generated when

both the TIE and the TDE bits in the ESSI status register are set. When TIE

is cleared, the transmit interrupt is disabled. The transmit interrupt is

documented in Section 7.3.3. When data is written to the data registers of

the enabled transmitters or to the TSR, it clears TDE and also clears the

interrupt. Transmit interrupts with exception conditions have higher priority

than normal transmit data interrupts. If the transmitter underrun error (TUE)

bit is set (signaling that an exception has occurred) and the TEIE bit is set,

the ESSI requests an SSI transmit data with exception interrupt from the

interrupt controller.

DSP56303 Scheda tecnica(PDF) 150 Page - Freescale Semiconductor, Inc

DSP56303 Scheda tecnica(HTML) 150 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL