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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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DSP56303 Scheda tecnica(PDF) 198 Page - Freescale Semiconductor, Inc |
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DSP56303 Scheda tecnica(HTML) 198 Page - Freescale Semiconductor, Inc |
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198 / 292 page  DSP56303 User’s Manual, Rev. 2 9-6 Freescale Semiconductor Triple Timer Module set. If the TCSR[TRM] bit is set, the counter is reloaded with the TLR value at the next timer clock and the count is resumed. If TCSR[TRM] is cleared, the counter continues to increment on each timer clock signal. This process repeats until the timer is disabled. Figure 9-3. Timer Mode (TRM = 1) Figure 9-4. Timer Mode (TRM = 0) Mode 0 (internal clock, no timer output): TRM = 1 N = write preload M = write compare TE Clock (CLK/2 or prescale CLK) TLR TCPR TCF (Compare Interrupt if TCIE = 1) Counter (TCR) first event last event M 0 N N + 1 M N N + 1 N Mode 0 (internal clock, no timer output): TRM = 0 N = write preload M = write compare TE Clock (CLK/2 or prescale CLK) TLR TCPR TCF (Compare Interrupt if TCIE = 1) Counter (TCR) first event last event M 0N N + 1 M 0 1 N M + 1 TOF (Overflow Interrupt if TCIE = 1) |
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