DSP56303 datasheet(200/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

9-8

Freescale Semiconductor

Triple Timer Module

9.3.1.3 Timer Toggle (Mode 2)

In Mode 2, the timer periodically toggles the polarity of the TIO signal. When the timer is

enabled, the TIO signal is loaded with the value of the TCSR[INV] bit. When the counter value

matches the value in the TCPR, the polarity of the TIO output signal is inverted. TCSR[TCF] is

set, and a compare interrupt is generated if the TCSR[TCIE] bit is set. If the TCSR[TRM] bit is

set, the counter is loaded with the value of the TLR when the next timer clock is received, and the

count resumes. If the TRM bit is cleared, the counter continues to increment on each timer clock.

This process repeats until the timer is cleared (disabling the timer). The TCPR[TLR] value sets

the delay between starting the timer and toggling the TIO signal. To generate output signals with

a delay of X clock cycles between toggles, set the TLR value to X/2, and set the TCSR[TRM] bit.

This process repeats until the timer is disabled (that is, TCSR[TE] is cleared).

Figure 9-6. Pulse Mode (TRM = 0)

Bit Settings

Mode Characteristics

TC3

TC2

TC1

TC0

Mode

Name

Function

TIO

Clock

Toggle

Timer

Output

Internal

Mode 1 (internal clock): TRM = 0

N = write preload

M = write compare

(CLK/2 or prescale CLK)

TLR

TCPR

TCF (Compare Interrupt if TCIE = 1)

first event

pulse width =

timer clock

period

TIO pin (INV = 0)

TIO pin (INV = 1)

TOF (Overflow Interrupt if TCIE = 1)

Counter (TCR)

N + 1

M + 1

Clock

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