TMP93CS32F datasheet(9/180 Pages) TOSHIBA

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TMP93CS32

2004-02-10

93CS32-7

Operation

This section describes the functions and basic operational blocks of TMP93CS32 devices.

See the 7. Points of Concern and Restriction for the using notice and restrictions for each block.

3.1

CPU

The TMP93CS32 device has a built-in high-performance 16-bit CPU (900/L CPU). (For CPU

operation, see TLCS-900/L CPU in the previous section).

This section describes CPU functions unique to the TMP93CS32 that are not described in the

previous section.

3.1.1

Reset

When resetting the TMP93CS32 microcontroller, ensure that the power supply voltage is

within the operating voltage range, and that the internal high-frequency oscillator has

stabilized. Then set the RESET input to Low level at least for 10 system clocks (16 µs at 20

MHz). Thus, when turn on the switch, be set to the power supply voltage is within the

operating voltage range, and that the internal high-frequency oscillator has stabilized.

Then hold the RESET input to Low level at least for 10 system clocks.

Clock gear is initialized 1/16 mode by Reset operation. It means that the system clock

mode fSYS is set to fc/32 (= fc/16 × 1/2).

When reset is accepted, the CPU sets as follows:

•

Program Counter (PC) according to Reset Vector that is stored FFFF00H to FFFF02H.

<7:0>

← Data in location FFFF00H

<15:8> ← Data in location FFFF01H

<23:16> ← Data in location FFFF02H

•

Stack pointer (XSP) for system mode to 100H.

•

IFF2 to 0 bits of status register to 111. (Sets mask register to interrupt level 7.)

•

MAX bit of status register to 1. (Sets to maximum mode)

•

Bits RFP2 to 0 of status register to 000. (Sets register banks to 0.)

When reset is released, instruction execution starts from PC (reset vector). CPU internal

registers other than the above are not changed.

When reset is accepted, processing for built-in I/Os, ports, and other pins is as follows:

•

Initializes built-in I/O registers as per specifications.

•

Sets port pins (Including pins also used as built-in I/Os) to general-purpose

input/output port mode.

•

Pulls up the CLK pin to “High” level.

•

Sets the ALE pin to high impeadance (High-Z).

Note 1: By resetting, register in the CPU except program counter (PC), status register (SR) and

stack pointer (XSP) and the data in internal RAM are not changed.

Note 2: The CLK pin is pulled up to “High” level during reset. When the voltage is put down

externally, there is possible to cause malfunctions.

Figure 3.1.1 shows the reset timing chart of TMP93CS32.

3.1.2

AM8/ AM16 Pin

Set this pin to “H”. After reset, the CPU accesses the internal ROM with 16-bit bus width.

The bus width when the CPU accesses an external area is set by bus width/wait control

registers and the registers of Port 1. (The value “H”of this pin is ignored and the value set

by register is active.) For details, see the bus width/wait control registers in section 3.6.3.

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