STR750FV0 datasheet(49/84 Pages) STMICROELECTRONICS

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STR750Fxx STR751Fxx STR752Fxx STR755Fxx

Electrical parameters

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PLL characteristics

Subject to general operating conditions for VDD_IO, and TA.

Internal RC oscillators (FREEOSC & LPOSC)

Subject to general operating conditions for VDD_IO, and TA.

Table 24.

PLL characteristics

Symbol

Parameter

Test Conditions

Value

Unit

Min

Typ

Max(1)

Data based on product characterisation, not tested in production.

fPLL_IN

PLL input clock

4.0

MHz

PLL input clock duty cycle

fPLL_OUT

PLL multiplier output clock

fPLL_INx 24

165

MHz

fVCO

VCO frequency range

When PLL

operates (locked)

336

960

MHz

tLOCK

PLL lock time

300

µs

∆tJITTER1(2)(3)

Refer to jitter terminology in : PLL characteristics on page 47 for details on how jitter is specified.

The jitter specification holds true only up to 50mV (peak-to-peak) noise on VDDA_PLL and V18 supplies.

Jitter will increase if the noise is more than 50mV. In addition, it assumes that the input clock has no jitter.

Single period jitter (+/-3

Σ peak

to peak)

fPLL_IN = 4 MHz

(4)

VDD_IO is stable

The PLL parameters (MX1, MX0, PRESC1, PRESC2) must respect the constraints described in: PLL

characteristics on page 47.

+/-250

∆tJITTER2(2)(3)

Long term jitter (+/-3

Σ peak to

peak)

fPLL_IN = 4 MHz

(4)

VDD_IO is stable

+/-2.5

∆tJITTER3(2)(3)

Cycle to cycle jitter (+/-3

Σ peak

to peak)

fPLL_IN = 4 MHz

(4)

VDD_IO is stable

+/-500

Table 25.

Internal RC oscillators (FREEOSC & LPOSC)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fCK_FREEOSC FREEOSC Oscillator Frequency

MHz

fCK_LPOSC

LPOSC Oscillator Frequency

150

300

500

kHz

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