25 / 60 page
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
JUNE, 2000, VERSION 1.2
25
COPYRIGHT
©
© 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
6.2.7 SP - Status Port
Status Port Low (E)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
FIFO_ST
CACQ_ST
Status Port High (F)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Reg
Bit#
Bit Name
Description
E
0
CACQ_ST
Cache Status. Status of horizontal downscaler cache (=1 if over
flowed).
E
1
FIFO_ST
FIFO Status. Output FIFO status (=1 if over/under flowed).
Notes:
FIFO Status:
FS450 does not have a frame memory. In FS450 the scaled input data rate and the output data rates are the
same. The FIFO takes up the slack during the asynchronous horizontal blanking interval of the input and output.
The FIFO depth (1024) is only slightly larger that the 720 output pixels required to form a CCIR 601 data stream.
The extra pixels are used for data overrun protection.
At the coincidence of a Filtered Horizontal and Vertical Start, the input and output FIFO pointers are reset to the to
beginning of the memory and data writes commence. Next, 24 output clock cycles after the Filtered Horizontal and
Vertical Start occur, the CCIR 656 Timing Generator issues a FIFO Horizontal and Vertical Start. This causes the
Horizontal Upscaler to issue a TV read and the FIFO starts to read data.
If a data overrun occurs, the offending FIFO’s pointer is halted and black is output to the Horizontal Upscaler. Also,
the FIFO data overrun flag is set.
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