FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
JUNE, 2000, VERSION 1.2
57
COPYRIGHT
©
© 1999,2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORM ATION
8.3 Switching Characteristics
Parameter
Conditions
Min
Typ2
Max
Unit
Clocks
fCKIN
TV Encoder Reference Clock Frequency
27.0
MHz
fXTOL
TV Reference Clock Frequency Tolerance
30
50
3
ppm
tPWHT
TV Reference Clock Pulse Width, HIGH
15.0
ns
tPWLT
TV Reference Clock Pulse Width, LOW
15.0
ns
fPCKIN
VGA Clock Positive Edge Frequency
40/60 duty cycle
27.0
85.0
MHz
fNCKIN
VGA Clock Negative Edge Frequency
40/60 duty cycle
27.0
85.0
MHz
fCORE
VGA Core Frequency
4
50.0
MHz
fVCKO
VGA Clock Output
27.0
85.0
MHz
tJIT-VCK VGA Clock Output Jitter (peak-to-peak)
over a cycle
200
ps
fPLLREF PLL Reference Clock Frequency
24
100
kHz
M
PLL Numerator
500
1200
tPWHV
VGA Clock Positive Edge Pulse Width, HIGH
5.0
tPWLV
VGA Clock Negative Edge Pulse Width, LOW
5.0
Reset
Assert fCKIN cycles on RESET\ to reset the part
16
Clocks
Digital RGB Input Port
tPDH
VGA_PCKIN to Data Hold Time
0
ns
tNDH
VGA_NCKIN to Data Hold Time
0
ns
tPSU
VGA_PCKIN to Data Setup Time
1.5
ns
tNSU
VGA_NCKIN to Data Setup Time
1.5
ns
CCIR 656 Video Input and Output Port
tTDH
TV_CKIN to Data Hold Time
0
ns
tTSU
TV_CKIN to Data Setup Time
10.0
ns
tTDO
TV_CKIN to Data Out Delay
24.0
ns
Serial Microprocessor Interface
tDAL
SCL Pulse Width, LOW
1.3
µs
tDAH
SCL Pulse Width, HIGH
0.6
µs
tSTAH
SDA Start Hold Time
0.6
µs
tSTASU SCL to SDA Setup Time (Stop)
0.6
µs
tSTOSU SCL to SDA Setup Time (Start)
0.6
µs
tBUFF
SDA Stop Hold Time Setup
1.3
µs
tDSU
SDA to SCL Data Setup Time
300
ns
tDHO
SDA to SCL Data Hold Time
300
ns
Notes:
1. GTL outputs are open drain, intended to drive 31 ohm termination from 1.8 volts.
2. Values shown in Typ column are typical for VDD = +3.3V and TA = 25°C
3. TV subcarrier acceptance band is
± 300 Hz.
4. VGA Core Frequency = VGA Clock Frequency/(UIM_DEC+1)
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