DP83849CVSSLASHNOPB datasheet(37/100 Pages) TI2

37 / 100 page

www.national.com

5.2 ESD Protection

Typically, ESD precautions are predominantly in effect

when handling the devices or board before being installed

in a system. In those cases, strict handling procedures

need be implemented during the manufacturing process to

greatly reduce the occurrences of catastrophic ESD

events. After the system is assembled, internal compo-

nents are less sensitive from ESD events.

The network interface pins are more susceptible to ESD

events.

5.3 Clock In (X1) Requirements

The DP83849C supports an external CMOS level oscillator

source or a crystal resonator device.

Oscillator

If an external clock source is used, X1 should be tied to the

clock source and X2 should be left floating.

Specifications for CMOS oscillators: 25 MHz in MII Mode

and 50 MHz in RMII Mode are listed in Table 14 and Table

15.

Crystal

A 25 MHz, parallel, 20 pF load crystal resonator should be

used if a crystal source is desired. Figure 13 shows a typi-

cal connection for a crystal resonator circuit. The load

capacitor values will vary with the crystal vendors; check

with the vendor for the recommended loads.

The oscillator circuit is designed to drive a parallel reso-

nance AT cut crystal with a minimum drive level of 100

µW

and a maximum of 500

µW. If a crystal is specified for a

lower drive level, a current limiting resistor should be

placed in series between X2 and the crystal.

As a starting point for evaluating an oscillator circuit, if the

requirements for the crystal are not known, CL1 and CL2

should be set at 33 pF, and R1 should be set at 0Ω.

Specification for 25 MHz crystal are listed in Table 16.

Figure 13. Crystal Oscillator Circuit

CL2

CL1

Table 14. 25 MHz Oscillator Specification

Parameter

Min

Typ

Max

Units

Condition

Frequency

MHz

Frequency

Tolerance

+50

ppm

Operational Temperature

Frequency

Stability

+50

ppm

1 year aging

Rise / Fall Time

nsec

20% - 80%

Jitter

8001

psec

Short term

Jitter

8001

psec

Long term

Symmetry

40%

60%

Duty Cycle

1 This limit is provided as a guideline for component selection and to guaranteed by production testing.

Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance.

DP83849CVS/NOPB Scheda tecnica(PDF) 37 Page - Texas Instruments

DP83849CVS/NOPB Scheda tecnica(HTML) 37 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Scheda tecnica Scarica

Link URL