DP83849CVSSLASHNOPB datasheet(64/100 Pages) TI2

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7.2.4 RMII and Bypass Register (RBR)

This register configures the RMII/MII Interface Mode of operation. This register controls selecting MII or RMII mode for

Receive or Transmit. In addition, several additional bits are included to allow datapath selection for Transmit and Receive

in multiport applications.

Table 36. RMII and Bypass Register (RBR), addresses 17h

Bit

Bit Name

Default

Description

SIM_WRITE

0, RW

Simultaneous Write:

Setting this bit in port A register space enables simultaneous write

to Phy registers in both ports. Subsequent writes to port A registers

will write to registers in both ports A and B.

1 = Simultaneous writes to both ports

0 = Per-port write

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

DIS_TX_OPT

0, RW

Disable RMII TX Latency Optimization:

Normally the RMII Transmitter will minimize the transmit latency by

realigning the transmit clock with the Reference clock phase at the

start of a packet transmission. Setting this bit will disable Phase re-

alignment and ensure that IDLE bits will always be sent in multiples

of the symbol size. This will result in a larger uncertainty in RMII

transmit latency.

12:9

RESERVED

RESERVED:

Must be zero

PMD_LOOP

0, RW

PMD Loopback:

0= Normal Operation

1= Remote (PMD) Loopback

Setting this bit will cause the device to Loopback data received

from the Physical Layer. The loopback is done prior to the MII or

RMII interface. Data received at the internal MII or RMII interface

will be applied to the transmitter. This mode should only be used if

RMII mode is enabled.

7:6

RESERVED

RESERVED:

Must be zero

RMII_MODE

Strap, RW

Reduced MII Mode:

0 = Standard MII Mode

1 = Reduced MII Mode

RMII_REV1_0

0, RW

Reduced MII Revision 1.0:

0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet

to indicate deassertion of CRS.

1 = (RMII revision 1.0) CRS_DV will remain asserted until final data

is transferred. CRS_DV will not toggle at the end of a packet.

RX_OVF_STS

0, RO/COR

RX FIFO Over Flow Status:

0 = Normal

1 = Overflow detected

RX_UNF_STS

0, RO/COR

RX FIFO Under Flow Status:

0 = Normal

1 = Underflow detected

1:0

ELAST_BUF[1:0]

01, RW

Receive Elasticity Buffer:

This field controls the Receive Elasticity Buffer which allows for fre-

quency variation tolerance between the 50MHz RMII clock and the

recovered data. See Section 3.2 for more information on Elasticity

Buffer settings in RMII mode.

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