FN8808 datasheet(36/44 Pages) RENESAS

36 / 44 page

ISL78227

FN8808 Rev.6.02

Page 36 of 43

Feb 28, 2025

This matches with the physics of the power devices that normally

have higher transient peak current rating and lower average

current ratings. The OC1 provides protection against the transient

peak current. The CC controls the average current with slower

response, but with much more accurate control of the maximum

power the system has to handle at overloading conditions.

1. When fast changing overloading occurs, because VIMON has

a sensing delay of RIMON*CIMON, CC does not trip at the

initial transient load current until it reaches the CC reference

of 1.6V. OC1 is triggered at the beginning to limit the inductor

peak current cycle-by-cycle.

2. After the delay of RIMON*CIMON, when VIMON reaches the CC

reference of 1.6V, CC control starts to work and limit duty

cycles to reduce the inductor current and keep the sum of the

two phases’ inductor currents constant. The time constant of

the RIMON*CIMON is typically on the order of 10 times slower

than the voltage loop bandwidth so that the two loops do not

interfere with each other.

CC loop is active at the beginning of soft-start.

From Equations 13 and 14 on page 31, the constant current

control current threshold level for the total 2-phase boost input

current can be calculated by Equation 23.

Average Overcurrent Fault (OC_AVG) Protection

The ISL78227 monitors the IMON pin voltage (which represents

the boost total input average current signal) to detect if the

Average Overcurrent (OC_AVG) fault occurs. As shown in Figure 3

on page 7, the comparator CMP_OCAVG compares VIMON to 2V

threshold to detect this fault. This fault detection is active at the

beginning of soft-start (t5 as shown in Figure 58 on page 29).

When VIMON is higher than 2V, the OC_AVG fault is triggered. The

ISL78227 responds with fault protection actions to shut down

the PWM switching and enters either Hiccup or Latch-off mode,

depending on HIC/LATCH pin configuration as described in

“Selectable Hiccup or Latch-Off Fault Response” on page 33 and

Table 3 on page 34.

Under the selection of Hiccup response for the OC_AVG fault,

when the IMON voltage falls to lower than the 2V threshold, the

device returns to normal switching through Hiccup soft-start.

From Equations 13 and 14 on page 31, the OC_AVG fault’s

current threshold level for the total 2-phase boost input current

can be calculated using Equation 24.

Because the Constant Current Loop uses the same IMON signal

and has a lower threshold (1.6V) than the OC_AVG threshold (2V),

the OC_AVG can hardly be tripped. The CC loop limits the IMON

signal around 1.6V, which is below 2V. Generally, the OC_AVG

functions as a worst-case backup protection.

INTERNAL DIE OVER-TEMPERATURE PROTECTION

The ISL78227 is disabled if the junction temperature reaches

+160°C (typical). A +15°C hysteresis ensures that the device

restarts with soft-start when the junction temperature falls below

+145°C (typical).

Internal 5.2V LDO

The ISL78227 has an internal LDO with input at VIN and a fixed

5.2V/100mA output at PVCC. The internal LDO tolerates an input

supply range of VIN up to 55V (60V absolute maximum). A 10µF,

10V or higher X7R type of ceramic capacitor is recommended

between PVCC to GND. At low VIN operation when the internal

LDO is saturated, the dropout voltage from the VIN pin to the

PVCC pin is typically 0.3V under 80mA load at PVCC, as shown in

the “Electrical Specifications” table on page 9. This is one of the

constraints to estimate the required minimum VIN voltage.

The output of this LDO is mainly used as the bias supply for the

gate drivers. With VCC connected to PVCC as in the typical

application, PVCC also supplies other internal circuitry. To provide

a quiet power rail to the internal analog circuitry, it is

recommended to place an RC filter between PVCC and VCC. A

minimum of 1µF ceramic capacitor from VCC to ground should

be used for noise decoupling purpose. Because PVCC is providing

noisy drive current, a small resistor (10Ω or smaller) between the

PVCC and VCC helps to prevent the noises from interfering from

PVCC to VCC.

Figure 62 shows the internal LDO output voltage (PVCC)

regulation versus its output current. The PVCC drops to 4.5V

(typical) when the load is 195mA (typical) because of the LDO

current-limiting circuits. When the load current further increases,

the voltage drops further and finally enters current foldback

mode where the output current is clamped to 100mA (typical). At

the worst case when LDO output is shorted to ground, the LDO

output is clamped to 100mA.

Based on the junction to ambient thermal resistance, RJA, of the

package, the maximum junction temperature should be kept below

+125°C. However, the power losses at the LDO need to be

considered, especially when the gate drivers are driving external

MOSFETs with large gate charges. At high VIN, the LDO has

significant power dissipation that may raise the junction

temperature where the thermal shutdown occurs.

IINCC

1.6

RIMON

------------------- 17 10



–







 RSET

RSEN

---------------- 8 A

 



(EQ. 23)

IINOCAVG

RIMON

------------------- 17 10



–







 RSET

RSEN

---------------- 8 A

 



(EQ. 24)

FIGURE 62. INTERNAL LDO OUTPUT VOLTAGE vs LOAD

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0.00

0.05

0.10

0.15

0.20

0.25

IOUT_PVCC (A)

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