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FN8808 Scheda tecnica(PDF) 39 Page - Renesas Technology Corp

Il numero della parte FN8808
Spiegazioni elettronici  2-Phase Boost Controller with Integrated Drivers
PDF  44 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

FN8808 Scheda tecnica(HTML) 39 Page - Renesas Technology Corp

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ISL78227
FN8808 Rev.6.02
Page 39 of 43
Feb 28, 2025
TRANSFER FUNCTION FROM VC TO VOUT
Transfer function from error amplifier output VC to output voltage
VOUT Gvcvo(s) can be expressed as Equation 33.
The expressions of the poles and zeros are listed below:
where:
• N is the number of phases, RESR is the output capacitor’s
Equivalent Series Resistance (ESR) of the total capacitors,
RLOAD is the load resistance, Leq is the equivalent inductance
for multiphase boost with N number of phases, and L is each
phase’s inductor’s inductance.
• KISEN is the current sense gain as shown in Equation 34,
where RSENx and RSETx are per-phase current sense resistors
and setting resistors described in “Current Sense for Individual
Phase - ISENX” on page 31.
• Se/Sn is the gain of the selected compensating slope over the
sensed inductor current up-ramp. It can be calculated in
Equation 35, where KSLOPE is the gain of selected
compensating slope over the sensed IL down slope (refer to
Equation 15 on page 32).
Equation 33 shows that the system is mainly a single order
system plus a Right Half Zero (RHZ), which commonly exists for
boost converters. The main pole ωpPS is determined by load and
output capacitance and the ESR zero ωESR is the same as the
buck converter.
Because the ωRHZ changes with load, typically the boost
converter crossover frequency is set 1/5 to 1/3 of the ωRHZ
frequency.
The double pole ωn is at half of the fSW and has minimum
effects at crossover frequency for most of the cases when the
crossover frequency is fairly low.
FIGURE 64. CONCEPTUAL BLOCK DIAGRAM OF PEAK CURRENT MODE CONTROLLED BOOST REGULATOR
-
+
Gm
VREF
VOUT
RCP
CCP2
FB
COMP
RFB2
RFB1
R1
C1
CCP1
ROEA
-
+
-
+
Gm
SLOPE
VIN
RSEN
VOUT
RLOAD
Resr
COUT
L
Gvcvo(s)
He2(s)
He1(s)
Vc
Vfb
RSET
FIGURE 65. CONCEPTUAL CONTROL BLOCK DIAGRAM
Gvcvo(s)
CURRENT MODE
CONTROL +POWER STAGE
He2(s)
ERROR AMP
+
-
VOUT
Vfb
Vc
He1(s)
VREF
Vfb
Gvcvo s
 
KDC
1
s
esr
------------
+
1
s
RHZ
---------------
1
s
pPS
----------------
+
1
s
Qp n
-------------------
s
n
-------
 2
+
+
---------------------------------------------------------------------------------------------
=
(EQ. 33)
KDC
RLOAD 1 D
2 K
 ISEN
-------------------------------------------
=
RHZ
RLOAD 1 D
2
Leq
----------------------------------------------
=
esr
1
COUT Resr
---------------------------------
=
pPS
2
COUT RLOAD
-----------------------------------------
=
Qp
1
1 D
Se
Sn
-------
0.5 D
+
--------------------------------------------------------------------
=
n  fSW
=
Leq LN----
=
KISEN
RSENx 6500
N R
 SETx
-------------------------------------
=
(EQ. 34)
(EQ. 35)
Se
Sn
-------
KSLOPE
VOUT
VIN
---------------- 1
=



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