ISL78227

FN8808 Rev.6.02

Page 13 of 43

Feb 28, 2025

NEGATIVE CURRENT CYCLE-BY-CYCLE LIMITNG (OC_NEG)

Negative Current Cycle-by-Cycle Limit

Threshold for Individual Phase

VOC_NEG

Negative Current Cycle-by-Cycle Limit

(IOC_NEG_TH = -48µA, compared with

ISENx).

Measures the voltage threshold before

RSETx at CSA Inputs (equivalent to the

voltage across the current sense shunt

resistor), RSET = 665Ω (0.1%)

-32

mV

AVERAGE CONSTANT CURRENT CONTROL LOOP

IMON Current Accuracy

VRSENx=30mV, RSETx = 665Ω (0.1%),with

ISENxP/N pins biased at 4V or 55V

common-mode voltage

27.0

28.3

29.5

µA

IMON Offset Current

VRSENx = 0V, RSET = 665Ω (0.1%), with

ISENxP/N pins biased at 4V or 55V

common-mode voltage

16

17

18

µA

Constant Current Control Reference

Accuracy

VREFCC

Measure the IMON pin

1.575

1.600

1.625

V

AVERAGE OVERCURRENT FAULT PROTECTION OC_AVG, (Refer to “Average Overcurrent Fault (OC_AVG) Protection” on page 36 for details)

OC_AVG Fault Threshold at the IMON Pin

1.9

2.0

2.1

V

OC_AVG Fault Trip Delay

1

µs

GATE DRIVERS

UG Source Resistance

RUG_SOURCE

100mA source current, VBOOT - VPH = 4.4V

1.2

Ω

UG Source Current

IUG_SOURCE

VUG - VPH = 2.5V, VBOOT - VPH = 4.4V

2

A

UG Sink Resistance

RUG_SINK

100mA sink current, VBOOT - VPH = 4.4V

0.6

Ω

UG Sink Current

IUG_SINK

VUG - VPH = 2.5V, VBOOT - VPH = 4.4V

2.0

A

LG Source Resistance

RLG_SOURCE

100mA source current, PVCC = 5.2V

1.2

Ω

LG Source Current

ILG_SOURCE

VLG - PGND = 2.5V, PVCC = 5.2V

2.0

A

LG Sink Resistance

RLG_SINK

100mA sink current, PVCC = 5.2V

0.55

Ω

LG Sink Current

ILG_SINK

VLG - PGND = 2.5V, PVCC = 5.2V

3

A

UG to PH Internal Resistor

50

kΩ

LG to PGND Internal Resistor

50

kΩ

BOOT-PH UVLO Detection Threshold

2.8

3.0

3.2

V

BOOT-PH UVLO Detection Threshold

Hysteresis

0.09

0.15

0.22

V

Dead Time Delay - UG Falling to LG Rising

tDT1

CUG = CLG = OPEN, RDT = 10k (0.1%)

55

70

85

ns

Dead Time Delay - LG Falling to UG Rising

tDT2

CUG = CLG = OPEN, RDT = 10k (0.1%)

65

80

95

ns

Dead Time Delay - UG Falling to LG rising

tDT1

CUG = CLG = OPEN, RDT = 18.2kΩ (0.1%)

85

100

115

ns

Dead Time Delay - LG Falling to UG Rising

tDT2

CUG = CLG = OPEN, RDT = 18.2kΩ (0.1%)

95

110

125

ns

Dead Time Delay - UG Falling to LG Rising

tDT1

CUG = CLG = OPEN, RDT = 50kΩ (0.1%)

185

210

240

ns

Dead Time Delay - LG Falling to UG Rising

tDT2

CUG = CLG = OPEN, RDT = 50kΩ (0.1%)

205

230

260

ns

Dead Time Delay - UG Falling to LG Rising

tDT1

CUG = CLG = OPEN, RDT = 64.9kΩ (0.1%)

235

265

295

ns

Dead Time Delay - LG Falling to UG Rising

tDT2

CUG = CLG = OPEN, RDT = 64.9kΩ (0.1%)

260

290

320

ns

Electrical Specifications Refer to Figure 3 on page 7 and Typical Application Schematics (page 8). Operating conditions unless

otherwise noted: VIN = 12V, VPVCC = 5.2V and VVCC = 5.2V, TA = -40°C to +125°C (Note 7). Typical values are at TA = +25°C. Boldface limits apply across

the operating temperature range, -40°C to +125°C. (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

(Note 6)

TYP

MAX

(Note 6) UNIT