MB85RS2MTY(AEC-Q100 Compliant)

12

DS501-00061-3v1-E



SSWR

The SSWR command writes data to special sector (a special region of 256 Byte in FeRAM). SSWR op-code,

arbitrary 24 bits address and 8-bit writing data are input to SI. The 16-bit upper address is invalid. When

input of 8-bit writing data is completed, it starts writing data to special sector. Risen CS will terminate the

SSWR command, but if you continue the writing data for each before CS rising, it is possible to continue

writing with automatic address increment. When it reaches the most significant address, roll over is not

happen, the data hereafter is ignored.

The data in special sector is stable between before and after reflow. Refer “ REFLOW CONDITIONS AND

FLOOR LIFE” for the reflow condition.



SSRD

The SSRD command reads data from special sector (a special region of 256 Byte in FeRAM). SSWR op-

code and arbitrary 24 bits address are input to SI. The 16-bit upper address is invalid. Then, 8-cycle clock

is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid.

When CS is risen, the SSRD command is completed, but keeps on reading with automatic address increment

which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches

the most significant address, roll over is not happen.

The data in special sector is stable between before and after reflow. Refer “ REFLOW CONDITIONS AND

FLOOR LIFE” for the reflow condition.

CS

SCK

Data In

SI

MSB

LSB MSB

LSB

High-Z

10 11

0123456789

24 25 26

31 32

23

27 28 29 30

33 34 35 36 37 38 39

0100001

3

0 XXXX

6

2 1 0

SO

X 7

54

3210

7654

24 bit addresses

ope. code

CS

SCK

SI

Invalid

MSB

LSB

MSB

Data Out

LSB

High-Z

Invalid

45

0123

26 27

6 7 8 9 10 11

23 24 25

38 39

28 29 30 31 32 33 34 35 36 37

01001011 X

32

XXX

6

X7

54

SO

76

3

10

54

210

24 bit addresses

ope. code