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MB85RS2MTY Scheda tecnica(PDF) 21 Page - RAMXEED LIMITED |
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MB85RS2MTY Scheda tecnica(HTML) 21 Page - RAMXEED LIMITED |
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21 / 38 page ![]() MB85RS2MTY(AEC-Q100 Compliant) DS501-00061-3v1-E 21 POWER ON/OFF SEQUENCE In case relative short VDD pulse whose peak level is beyond 1.7 is applied, please set VDD falling time, tf, longer than 0.4ms/V. (When VDD rises beyond 1.7V, and falls just after, if this term is very short the device may loose its function.). If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed. Parameter Symbol Value Unit Condition VDD Min Max CS level hold time at power OFF tpd 400 ns 1.8V to 2.7V 0 2.7V to 3.6V CS level hold time at power ON tpu 450 s Power supply rising time tr 0.05 ms/V Power supply falling time tf 0.1 ms/V CS >VDD × 0.7 ∗ tpd tpu tr tf VIL (Max) 1.7 V VIH (Min) VDD (Min) VDD CS : don't care CS >VDD × 0.7 ∗ CS CS VIL (Max) 1.7 V VIH (Min) VDD (Min) VDD VSS VSS * : CS (Max) < VDD 0.5 V |
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