IS46TR16640C datasheet(13/89 Pages) ISSI

13 / 89 page

IS43/46TR16640C, IS43/46TR16640CL

IS43/46TR81280C, IS43/46TR81280CL

Integrated Silicon Solution, Inc. – www.issi.com –

Rev. E

12/27/2024

operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or

synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock.

Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON or tAOF parameters. During

tDLLK, CKE must continuously be registered high. DDR3 SDRAM does not require DLL for any Write operation, except

when RTT_WR is enabled and the DLL is required for proper ODT operation. For more detailed information on DLL

Disable operation refer to “DLL-off Mode”.

The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by

continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode

The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR, MR2 {A10,

A9} = {0,0}, to disable Dynamic ODT externally.

2.3.3.2 Output Driver Impedance Control

The output driver impedance of the DDR3 SDRAM device is selected by MR1 (bits A1 and A5) as shown in Figure 2.3.3.

2.3.3.3 ODT Rtt Values

DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal termination

value Rtt_Nom is programmed in MR1. A separate value (Rtt_WR) may be programmed in MR2 to enable a unique RTT

value when ODT is enabled during writes. The Rtt_WR value can be applied during writes even when Rtt_Nom is

disabled.

2.3.3.4 Additive Latency (AL)

Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidths in

DDR3 SDRAM. In this operation, the DDR3 SDRAM allows a read or write command (either with or without auto-

precharge) to be issued immediately after the active command. The command is held for the time of the Additive Latency

(AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL)

register settings. Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A

summary of the AL register options are shown in Table below.

Additive Latency (AL) Settings

0 (AL Disabled)

CL - 1

CL - 2

Reserved

NOTE: AL has a value of CL - 1 or CL - 2 as per the CL values programmed in the MR0 register

2.3.3.5 Write leveling

For better signal integrity, DDR3 memory module adopted fly-by topology for the commands, addresses, control signals,

and clocks. The fly-by topology has the benefit of reducing the number of stubs and their length, but it also causes flight

time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the Controller to maintain

tDQSS, tDSS, and tDSH specification. Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow the

controller to compensate for skew.

2.3.3.6 Output Disable

The DDR3 SDRAM outputs may be enabled/disabled by MR1 (bit A12) as shown in Figure 2.3.3. When this feature is

enabled (A12 = 1), all output pins (DQs, DQS, DQS#, etc.) are disconnected from the device, thus removing any loading

of the output drivers. This feature may be useful when measuring module power, for example. For normal operation, A12

should be set to ‘0’.

2.3.3.7 TDQS, TDQS#

TDQS (Termination Data Strobe) is a feature of X8 DDR3 SDRAM that provides additional termination resistance outputs

that may be useful in some system configurations. The TDQS function is available in X8 DDR3 SDRAM only and must be

disabled via the mode register A11=0 in MR1 for X16 configuration.

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