IS46TR16640C datasheet(73/89 Pages) ISSI

73 / 89 page

IS43/46TR16640C, IS43/46TR16640CL

IS43/46TR81280C, IS43/46TR81280CL

Integrated Silicon Solution, Inc. – www.issi.com –

Rev. E

12/27/2024

9.5 Address / Command Setup, Hold and Derating

For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the datasheet tIS(base)

and tIH(base) value to the

ΔtIS and ΔtIH derating value, respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS

Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the

first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate

line between shaded ‘VREF(dc) to ac region’, use nominal slew rate for derating value . If the actual signal is later than

the nominal slew rate line anywhere between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual

signal from the ac level to VREF (dc) level is used for derating value.

Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the

first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate

line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than

the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual

signal from the dc level to VREF (dc) level is used for derating value.

For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC. Although for slow slew

rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the

rising clock transition, a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in

between the values listed in the tables, the derating values may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

9.5.1 ADD/CMD Setup and Hold Base-Values for 1V/ns

DDR3/

DDR3L

Symbol

Reference

DDR3-

800

DDR3-

1066

DDR3-

1333

DDR3-

1600

DDR3-

1866

DDR3-

2133

Units

DDR3

tIS(base) AC175

VIH/L(ac)

200

125

tIS(base) AC150

VIH/L(ac)

350

275

190

170

tIS(base) AC135

VIH/L(ac)

tIS(base) AC125

VIH/L(ac)

150

135

tIH(base) DC100

VIH/L(dc)

275

200

140

120

100

DDR3L

tIS(base) AC160

VIH/L(ac)

215

140

tIS(base) AC135

VIH/L(ac)

365

290

205

185

tIS(base) AC125

VIH/L(ac)

150

135

tIH(base) DC90

VIH/L(dc)

285

210

150

130

110

105

Note:

(AC/DC referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate)

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