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TSC2004 Scheda tecnica(PDF) 7 Page - Texas Instruments |
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TSC2004 Scheda tecnica(HTML) 7 Page - Texas Instruments |
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7 / 62 page  www.ti.com TIMING REQUIREMENTS for Figure 1: I 2C Standard Mode (f SCL = 100kHz) (1) TSC2004 SBAS408E – JUNE 2007 – REVISED MARCH 2008 All specifications typical at –40 °C to +85°C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted. 2-WIRE STANDARD MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT SNSVDD ≥ 1.6V 10 µs Reset low time(2) tWL(RESET) 1.2V ≤ SNSVDD < 1.6V 13 µs SCL clock frequency fSCL 100 kHz Bus free time between a STOP and START tBUF 4.7 µs condition Hold time (repeated) START condition tHD, STA 4.0 µs Low period of SCL clock tLOW 4.7 µs High period of the SCL clock tHIGH 4.0 µs Setup time for a repeated START condition tSU, STA 4.7 µs Data hold time tHD, DAT 0 3.45 µs Data setup time tSU, DAT 250 ns Rise time of both SDA and SCL signals tR Cb = total bus capacitance 1000 ns Fall time of both SDA and SCL signals tF Cb = total bus capacitance 300 ns Setup time for STOP condition tSU, STO 4.0 µs Capacitive load for each bus line Cb Cb = total capacitance of one bus line in pF 400 pF Pulse width of spike suppressed tSP N/A N/A ns (1) All input signals are specified with tR = tF = 5ns (30% to 70% of I/OVDD) and timed from a voltage level of (VIL + VIH)/2. (2) Refer to Figure 38. TIMING REQUIREMENTS for Figure 1: I 2C Fast Mode (f SCL = 400kHz) (1) All specifications typical at –40 °C to +85°C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted. 2-WIRE FAST MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT SNSVDD ≥ 1.6V 10 µs Reset low time(2) tWL(RESET) 1.2V ≤ SNSVDD < 1.6V 13 µs SCL clock frequency fSCL 400 kHz Bus free time between a STOP and START tBUF 1.3 µs condition Hold time (repeated) START condition tHD, STA 0.6 µs Low period of SCL clock tLOW 1.3 µs High period of the SCL clock tHIGH 0.6 µs Setup time for a repeated START condition tSU, STA 0.6 µs Data hold time tHD, DAT 0 0.9 µs Data setup time tSU, DAT 100 ns Rise time of both SDA and SCL signals tR Cb = total bus capacitance 20 + 0.1 × C b 300 ns Fall time of both SDA and SCL signals tF Cb = total bus capacitance 20 + 0.1 × C b 300 ns Setup time for STOP condition tSU, STO 0.6 µs Capacitive load for each bus line Cb Cb = total capacitance of one bus line in pF 400 pF Pulse width of spike suppressed tSP 0 50 ns (1) All input signals are specified with tR = tF = 5ns (30% to 70% of I/OVDD) and timed from a voltage level of (VIL + VIH)/2. (2) Refer to Figure 38. Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): TSC2004 |
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