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RC19302A00AGNT#KD0 Scheda tecnica(PDF) 31 Page - Renesas Technology Corp |
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RC19302A00AGNT#KD0 Scheda tecnica(HTML) 31 Page - Renesas Technology Corp |
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31 / 62 page ![]() R31DS0210EU0106 Rev.1.06 Page 31 May 11, 2026 RC193xx Datasheet Figure 12. Test Load for PCIe Phase Jitter Measurements Table 30. Parameters for PCIe Jitter Measurement Clock Source L (cm) [1] 1. PCIe Gen5-7 specify L = 0cm for 32, 64 and 128GT/s. L = 25.4cm is more conservative. CAC (uF) ZOUTSEL_tri pin Zo (ohms) Rs (ohms) SMA100B 25.4 0.1 0 (85 ohms) 85 Internal 1 (100 ohms) 100 Internal Mid (34 ohms) None DUT Board CKIN+ CK+ DUT Chip CKIN- CK- Zo (differential) Rs Rs CK+ Clock Source CK- SMA Balun SMA L CAC CAC PNA 50 SMA |
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